J
Joe M. Jeddeloh
Researcher at Micron Technology
Publications - 29
Citations - 1080
Joe M. Jeddeloh is an academic researcher from Micron Technology. The author has contributed to research in topics: Semiconductor memory & Registered memory. The author has an hindex of 14, co-authored 29 publications receiving 1033 citations.
Papers
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Proceedings ArticleDOI
Hybrid memory cube new DRAM architecture increases density and performance
Joe M. Jeddeloh,Brent Keeth +1 more
TL;DR: The Hybrid Memory Cube is a three-dimensional DRAM architecture that improves latency, bandwidth, power and density and Heterogeneous die are stacked with significantly more connections, thereby reducing the distance signals travel.
Patent
Interface for high speed memory
TL;DR: In this paper, an interface circuit, which can form part of a memory device or a memory controller, includes a read circuit, a write circuit, and a clocking circuit.
Patent
Multi-serial interface stacked-die memory architecture
Joe M. Jeddeloh,Paul A. LaBerge +1 more
TL;DR: In this paper, the authors describe a system that can concurrently transfer a plurality of streams of commands, addresses, and data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch.
Patent
Memory devices and methods for managing error regions
TL;DR: Memory devices and methods for repartitioning the stack of memory dies and storing the new partitions in a memory map are described in this paper, where the authors also present a logic die and a stack of logic dies.
Patent
Variable memory refresh devices and methods
TL;DR: Memory devices and methods are described such as those that monitor and adjust characteristics for various different portions of a given memory device as discussed by the authors. Examples of different portions include tiles, or arrays, or dies.