This invention discloses a three-dimensional, high density package for integrated circuits for which integrated circuits are placed onto substrate layers and then stacked together. Techniques for interconnecting the layers to one another and for connecting the layers to external circuitry are also disclosed. Techniques for cooling the stack with heat sinks or fluid flow are also disclosed.

Three dimensional integrated circuit package

An ultra-thin level-one integrated circuit package with improved moisture penetration characteristics manufactured using a transfer molded casing with metallic lamination layers is provided. Additionally, a method and apparatus for providing a multiple-element modular package including a plurality of such level-one packages in horizontal or vertical stack configuration is provided.

Ultra high density integrated circuit packages method

Semiconductor chip assemblies incorporating flexible, sheet-like elements having terminals thereon overlying the front or rear face of the chip to provide a compact unit. The terminals on the sheet-like element are movable with respect to the chip, so as to compensate for thermal expansion. A resilient element such as a compliant layer interposed between the chip and terminals permits independent movement of the individual terminals toward the chip driving engagement with a test probe assembly so as to permit reliable engagement despite tolerances.

Semiconductor chip assemblies, methods of making same and components for same

Thin and durable level-one and level-two integrated circuit packages are provided. A thin and durable level-one package is achieved in one method involving a molding technique of evenly applying molding compound to an integrated circuit die element. The casing surrounding a die element may be reduced or eliminated in part to thin the level-one package provided any necessary steps are taken to ensure the integrity of the package. Moisture-barriers, as an example, may be provided to the upper and/or lower surfaces of the thin level-one package. Additionally, a thin level-one package may also be constructed with one or more metal layers to prevent warpage. These level-one packages may be aligned in a stacked configuration to form a thin and durable horizontal level-two package. Various thermal conductors may be thermally coupled to the level-two package to help dissipate heat.

Ultra high density integrated circuit packages

An implantable medical device with a ceramic enclosure has a novel multi-layered ceramic feedthrough substrate in place of a prior art glass-to-metal feedthrough substrate, leading to lower costs and a higher feedthrough density. Use in a metal enclosure is also disclosed.

Implantable ceramic enclosure for pacing, neurological, and other medical applications in the human body

A semiconductor device including a double cavity semiconductor chip carrier (100) which comprises a multilayer ceramic sandwich structure having a pair of semiconductor chip receiving cavities in the opposite faces thereof. The package enables mounting and electrical interconnection of a pair of semiconductor integrated circuit chips in a package of the same size as that for a single chip and having somewhat greater thickness. External terminals (93) on an outside face of the carrier are connected selectively by metallization paths (44, 53, 55, 83) integral with the carrier to chip mounting pads (41, 51) and to internal terminals (28) within the carrier. The internal terminals are disposed peripherally with respect to the chip cavities and adapted for interconnection with chip contact pads (26). Thus, a pair of unlike semiconductor integrated circuits can be interconnected in accordance with different patterns within a single package.

John Francis Gogal

Papers

Double cavity semiconductor chip carrier