A multilayer ceramic device suitable for use in surface mount decoupling applications may have a single capacitor or a capacitor array The device has a capacitor body defining a plurality of electrical terminals on an outer surface thereof The terminals are interdigitated such that a respective first polarity terminal will be adjacent to a respective second polarity terminal (and vice versa) The capacitor body contains a plurality of interleaved capacitor plates in opposed and spaced apart relation Capacitor plates of the first polarity are electrically connected to respective first polarity terminals via a plurality of lead structures Likewise, a plurality of lead structures electrically connect capacitor plates of the second polarity to respective second polarity terminals

Surface mount multilayer capacitor

A multi-layer capacitor includes first and second side-surface terminal electrodes alternately arranged on four side surfaces of a capacitor body. First and second major-surface terminal electrodes are arranged on a major surface of the capacitor body. First and second internal electrodes which are opposed to each other within the capacitor body are respectively electrically connected at ends thereof to the first and second side-surface terminal electrodes, and are also respectively electrically connected to the first and second major-surface terminal electrodes through via hole conductors. With this arrangement, the directions of the currents flowing within the multi-layer capacitor are diversified, and the lengths of current-carrying paths are shortened so as to achieve a very low ESL value.

Multi-layer capacitor, wiring board, and high-frequency circuit

A multi-layer capacitor is constructed to minimize equivalent series inductance (ESL) and includes first inner electrodes and second inner electrodes disposed opposite to each other. The first inner electrodes are electrically connected to a first outer terminal electrode via a first feed-through conductor and the second inner electrodes are electrically connected to a second outer terminal electrode via a second feed-through conductor. The first and second feed-through conductors are arranged in such a manner that magnetic fields induced by current flowing through the inner electrodes are cancelled. In addition, some of these feed-through conductors are arranged to define first and second peripheral feed-through conductors connected to the first and second inner electrodes at each periphery of the first and second inner electrodes.

Multi-layer capacitator, wiring substrate, decoupling circuit, and high-frequency circuit

Low inductance capacitors include electrodes that are arranged among dielectric layers and oriented such that the electrodes are substantially perpendicular to a mounting surface. Vertical electrodes are exposed along a device periphery to determine where termination lands are formed, defining a narrow and controlled spacing between the lands that is intended to reduce the current loop area, thus reducing the component inductance. Further reduction in current loop area and thus component equivalent series inductance (ESL) may be provided by interdigitated terminations. Terminations may be formed by various electroless plating techniques, and may be directly soldered to circuit board pads. Terminations may also be located on “ends” of the capacitors to enable electrical testing or to control solder fillet size and shape. Two-terminal devices may be formed as well as devices with multiple terminations on a given bottom (mounting) surface of the device. Terminations may also be formed on the top surface (opposite a designated mounting surface) and may be a mirror image, reverse-mirror image, or different shape relative to the bottom surface.

Multilayer ceramic capacitor with internal current cancellation and bottom terminals

A multilayer capacitor is constructed and arranged to significantly reduce an equivalent serial inductance (ESL) and includes a capacitor body in which first and second inner electrodes extend, respectively, so as to connect first and second end surfaces and first and second side surfaces First and second end surface terminal electrodes are provided on the first and second end surfaces Also, first and second side surface terminal electrodes are provided on the first and second side surfaces, respectively The widthwise dimension of the capacitor body is within a range of about 09 to about 11 times of the lengthwise dimension Also, when a represents a lengthwise dimension and a widthwise dimension of the capacitor body, and b represents widths of the first inner electrodes and the second inner electrodes, it is preferable that a and b are determined so as to have the relationship of: 045≦b/a≦090

Multilayer capacitor, electronic device and high frequency circuit using the same

A capacitor structure is described as having a plurality of dielectric materials located so that each dielectric material is in parallel between capacitor plates. The capacitor value of this structure is preset, therefore, for operation electrically at different specific temperatures. The description gives a specific stacked arrangement for the various dielectric materials in which this capacitor can be formed, as one example of that to which it is adaptable.

John Galvagni

Papers

Decoupling capacitor structure

Method of manufacturing a decoupling capacitor structure