An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

This updated version of the popular handbook further explains all aspects of physical vapor deposition (PVD) process technology from the characterizing and preparing the substrate material, through deposition processing and film characterization, to post-deposition processing. The emphasis of the new edition remains on the aspects of the process flow that are critical to economical deposition of films that can meet the required performance specifications, with additional information to support the original material. The book covers subjects seldom treated in the literature: substrate characterization, adhesion, cleaning and the processing. The book also covers the widely discussed subjects of vacuum technology and the fundamentals of individual deposition processes. However, the author uniquely relates these topics to the practical issues that arise in PVD processing, such as contamination control and film growth effects, which are also rarely discussed in the literature. In bringing these subjects together in one book, the reader can understand the interrelationship between various aspects of the film deposition processing and the resulting film properties. The author draws upon his long experience with developing PVD processes and troubleshooting the processes in the manufacturing environment, to provide useful hints for not only avoiding problems, but also for solving problems when they arise. He uses actual experiences, called 'war stories', to emphasize certain points. Special formatting of the text allows a reader who is already knowledgeable in the subject to scan through a section and find discussions that are of particular interest. The author has tried to make the subject index as useful as possible so that the reader can rapidly go to sections of particular interest. Extensive references allow the reader to pursue subjects in greater detail if desired. The book is intended to be both an introduction for those who are new to the field and a valuable resource to those already in the field. The discussion of transferring technology between R&D and manufacturing provided in Appendix 1, will be of special interest to the manager or engineer responsible for moving a PVD product and process from R&D into production. Appendix 2 has an extensive listing of periodical publications and professional societies that relate to PVD processing. The extensive Glossary of Terms and Acronyms provided in Appendix 3 will be of particular use to students and to those not fully conversant with the terminology of PVD processing or with the English language. This title is fully revised and updated to include the latest developments in PVD process technology. It includes 'War stories' drawn from the author's extensive experience emphasize important points in development and manufacturing. Appendices include listings of periodicals and professional societies, terms and acronyms, and material on transferring technology between R&D and manufacturing.

Handbook of physical vapor deposition (PVD) processing

Modern computer microprocessor chips are marvels of engineering complexity. For the current 45 nm technology node, there may be nearly a billion transistors on a chip barely 1 cm2 and more than 10 000 m of wiring connecting and powering these devices distributed over 9-10 wiring levels. This represents quite an advance from the first INTEL 4004B microprocessor chip introduced in 1971 with 10 μm minimum dimensions and 2 300 transistors on the chip! It has been disclosed that advanced microprocessor chips at the 32 nm node will have more than 2 billion transistors.1 For instance, Figure 1 shows a sectional 3D image of a 90 nm IBM microprocessor, containing several hundred million integrated devices and 10 levels of interconnect wiring, designated as the back-end-of-the-line (BEOL). Since the invention of microprocessors, the number of active devices on a chip has been exponentially increasing, approximately doubling every two years. This trend was first described in 1965 by Gordon Moore,2 although the original discussion suggested doubling the number of devices every year, and the phenomenon became popularly known as Moore’s Law. This progress has proven remarkably resilient and has persisted for more than 50 years. The enabler that has permitted these advances is known as scaling, that is, the reduction of minimum device dimensions by lithographic advances (photoresists, tooling, and process integration optimization) by ∼30% for each device generation.3 It allowed more active devices to be incorporated in a given area and improved the operating characteristics of the individual transistors. It should be emphasized that the earlier improvements in chip performance were achieved with very few changes in the materials used in the construction of the chips themselves. The increase of performance with scaling * Corresponding author. E-mail: gdubois@us.ibm.com. † IBM Almaden Research Center. ‡ Stanford University. Willi Volksen received his B.S. in Chemistry (magna cum laude) from New Mexico Institute of Mining and Technology in 1972 and his Ph.D. in Chemistry/Polymer Science from the University of Massachusetts, Lowell, in 1975. He then joined the research group of Prof. Harry Gray/Dr. Alan Rembaum at the California Institute of Technology as a postdoctoral fellow and upon completion of the one-year appointment joined Dr. Rembaum at the Jet Propulsion Laboratory as a Senior Chemist in 1976. In 1977 Dr. Volksen joined the IBM Research Division at the IBM Almaden Research Center in San Jose, CA, where he is an active research staff member in the Advanced Materials Group of the Science and Technology function.

Low dielectric constant materials.

An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.

Controllable ovonic phase-change semiconductor memory device and methods of fabricating the same

A comparative micro-cantilever study of the mechanical behavior of silicon based passivation films

"The Handbook of Multilevel Metallization for Integrated Circuits" answers and important need by pulling together in one volume a thorough technical summary of each of the key areas that make up a multilevel metal system. Included are associated design, analysis, materials, and manufacturing topics. The book serves three purposes. It functions as a good learning tool for the engineer newly assigned to work in metallization. It serves as a reference text for any MLM engineer, new or experienced, who wishes to refresh their memory. For someone who wants to further specialize in one topical areas, an extensive listing of references has been provided.

Handbook of multilevel metallization for integrated circuits : materials, technology, and applications

Metal step coverage is improved by utilizing a multiple step metallization process. In the first step, a thick portion of a metal layer is deposited on a semiconductor wafer at a cold temperature. The remaining amount of metal is deposited in a second step as the temperature is ramped up to allow for reflow of the metal layer through grain growth, recrystallization and bulk diffusion. The thick portion of the metal layer deposited at the cold temperature is of adequate thickness so that it remains continuous at the higher temperature and enhances via filling.

Multiple step metallization process

A method is provided for planarizing a multi-layer metal bonding pad. A first metal layer (13) is provided. A first dielectric layer (14) is provided with a multitude of vias (17) covering the first metal layer (13), thereby exposing portions of the first metal layer (13) through the multitude of vias (17) in the first dielectric (14). A second metal layer (18) is deposited on the first dielectric layer (14) making electrical contact to the first metal layer through the multitude of vias (17). Planarization of the second metal layer (18) is achieved by having the second metal layer (18) cover the first dielectric layer (14) and making contact through the vias (17).

Method for making a planar multi-layer metal bonding pad

An advanced 04 mu m BiCMOS technology has been developed for high-performance ASIC (application-specific integrated circuit) applications The technology consists of a core 33 V CMOS process featuring 04 mu m effective channel lengths into which a high-performance n-p-n device module has been integrated The ECL (emitter coupled logic) circuits are designed to operate with a conventional supply voltage of 52 V while the CMOS circuits are powered from an internally regulated 33 V supply The n-p-n device features trench isolation and a self-aligned polysilicon emitter-base structure with a 04 mu m final emitter width A peak Ft of 20 GHz and a minimum ECL delay of 41 ps at Ig=300 mu A have been achieved This technology features silicided polysilicon local interconnection and up to 4 layers of metallization A 51 mu m/sup 2/ 6T CMOS SRAM cell is available for applications requiring embedded SRAM >

An advanced 0.4 mu m BiCMOS technology for high performance ASIC applications

A residue-free plasma etch of high temperature aluminum copper metallization is provided by the use of a single plasma etcher. The metallization layer is covered by a protective oxide layer. This structure is then placed in the single etcher and a vacuum is established. The protective oxide layer is then etched and without breaking the vacuum or removing the structure from the etcher the metal layer is also etched. This results in the etched surface being residue-free.

John L. Freeman

Papers

Handbook of multilevel metallization for integrated circuits : materials, technology, and applications

Multiple step metallization process

Method for making a planar multi-layer metal bonding pad

An advanced 0.4 mu m BiCMOS technology for high performance ASIC applications

Residue-free plasma etch of high temperature AlCu