A modification of the nudged elastic band method for finding minimum energy paths is presented. One of the images is made to climb up along the elastic band to converge rigorously on the highest saddle point. Also, variable spring constants are used to increase the density of images near the top of the energy barrier to get an improved estimate of the reaction coordinate near the saddle point. Applications to CH4 dissociative adsorption on Ir~111! and H2 on Si~100! using plane wave based density functional theory are presented. © 2000 American Institute of Physics. @S0021-9606~00!71246-3#

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A climbing image nudged elastic band method for finding saddle points and minimum energy paths

An improved way of estimating the local tangent in the nudged elastic band method for finding minimum energy paths is presented. In systems where the force along the minimum energy path is large compared to the restoring force perpendicular to the path and when many images of the system are included in the elastic band, kinks can develop and prevent the band from converging to the minimum energy path. We show how the kinks arise and present an improved way of estimating the local tangent which solves the problem. The task of finding an accurate energy and configuration for the saddle point is also discussed and examples given where a complementary method, the dimer method, is used to efficiently converge to the saddle point. Both methods only require the first derivative of the energy and can, therefore, easily be applied in plane wave based density-functional theory calculations. Examples are given from studies of the exchange diffusion mechanism in a Si crystal, Al addimer formation on the Al(100) surfa...

Improved tangent estimate in the nudged elastic band method for finding minimum energy paths and saddle points

Electrons have a charge and a spin, but until recently these were considered separately. In classical electronics, charges are moved by electric fields to transmit information and are stored in a capacitor to save it. In magnetic recording, magnetic fields have been used to read or write the information stored on the magnetization, which 'measures' the local orientation of spins in ferromagnets. The picture started to change in 1988, when the discovery of giant magnetoresistance opened the way to efficient control of charge transport through magnetization. The recent expansion of hard-disk recording owes much to this development. We are starting to see a new paradigm where magnetization dynamics and charge currents act on each other in nanostructured artificial materials. Ultimately, 'spin currents' could even replace charge currents for the transfer and treatment of information, allowing faster, low-energy operations: spin electronics is on its way.

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The emergence of spin electronics in data storage

Wide-band-gap oxides such as SrTiO3 are shown to be critical tests of theories of Schottky barrier heights based on metal-induced gap states and charge neutrality levels. This theory is reviewed and used to calculate the Schottky barrier heights and band offsets for many important high dielectric constant oxides on Pt and Si. Good agreement with experiment is found for barrier heights. The band offsets for electrons on Si are found to be small for many key oxides such as SrTiO3 and Ta2O5 which limit their utility as gate oxides in future silicon field effect transistors. The calculations are extended to screen other proposed oxides such as BaZrO3. ZrO2, HfO2, La2O3, Y2O3, HfSiO4, and ZrSiO4. Predictions are also given for barrier heights of the ferroelectric oxides Pb1−xZrxTiO3 and SrBi2Ta2O9 which are used in nonvolatile memories.

Band offsets of wide-band-gap oxides and implications for future electronic devices

http://files.janapv.webnode.cz/200000097-8a03f8afdf/ex_bias_nano.pdf

Exchange bias in nanostructures

A low-power 1-Mb magnetoresistive random access memory (MRAM) based on a one-transistor and one-magnetic tunnel junction (1T1MTJ) bit cell is demonstrated. This is the largest MRAM memory demonstration to date. In this circuit, the magnetic tunnel junction (MTJ) elements are integrated with CMOS using copper interconnect technology. The copper interconnects are cladded with a high-permeability layer which is used to focus magnetic flux generated by current flowing through the lines toward the MTJ devices and reduce the power needed for programming. The 25-mm/sup 2/ 1-Mb MRAM circuit operates with address access times of less than 50 ns, consuming 24 mW at 3.0 V and 20 MHz. The 1-Mb MRAM circuit is fabricated in a 0.6-/spl mu/m CMOS process utilizing five layers of metal and two layers of poly.

A 1-Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects

Sputtered Ba1−xSrxTiO3 (BST) and SrTiO3 (STO) films and capacitors made with these dielectrics have been characterized with respect to physical and electrical properties. Specific capacitance values included a high of 96 fF/μm2 for BST films deposited of 600 °C and a high of 26 fF/μm2 for STO films deposited at 400 °C. Leakage current densities at 3.3 V for the most part varied from mid 10−8 to mid 10−6 A/cm2. All of the dielectrics are polycrystalline, although the lowest temperature STO films have a nearly amorphous layer which impacts their capacitance. Grain size increases with deposition temperature, which correlates to higher dielectric constants. The lattice parameter of the BST films is larger than that of bulk samples. Capacitance, leakage, breakdown, and lifetime results are reported.

Characterization of sputtered barium strontium titanate and strontium titanate-thin films

A method of fabricating GMR devices on a CMOS substrate structure with a semiconductor device formed therein. The method includes forming a dielectric system with a planar surface having a roughness in a range of 1 Å to 20 Å RMS on the substrate; disposing and patterning films of giant magneto-resistive material on the planar surface so as to form a memory cell; disposing a dielectric cap on the cell so as to seal the cell and provide a barrier to subsequent operations; forming vias through the dielectric cap and the dielectric system to interconnects of the semiconductor device; forming vias through the dielectric cap to the magnetic memory cell; and depositing a metal system through the vias to the interconnects and to the memory cell.

Method of fabricating GMR devices

"The Handbook of Multilevel Metallization for Integrated Circuits" answers and important need by pulling together in one volume a thorough technical summary of each of the key areas that make up a multilevel metal system. Included are associated design, analysis, materials, and manufacturing topics. The book serves three purposes. It functions as a good learning tool for the engineer newly assigned to work in metallization. It serves as a reference text for any MLM engineer, new or experienced, who wishes to refresh their memory. For someone who wants to further specialize in one topical areas, an extensive listing of references has been provided.

Handbook of multilevel metallization for integrated circuits : materials, technology, and applications

A low power 1 Mb Magnetoresistive Random Access Memory (MRAM) based on a 1-Transistor and 1-Magnetic Tunnel Junction (1T1MTJ) bit cell is demonstrated. This is the largest MRAM memory demonstration to date. In this circuit, MTJ elements are integrated with CMOS using copper interconnect technology. The copper interconnects are cladded with a high permeability layer which is used to focus magnetic flux generated by current flowing through the lines toward the MTJ devices and reduce the power needed for programming the bits. The 25 mm/sup 2/ 1 Mb MRAM circuit operates with address access times of less than 50 ns, consuming 24 mW at 3.0 V and 20 MHz. The circuit is fabricated in a 0.6 /spl mu/m CMOS process utilizing five layers of metal and two layers of poly.

Clarence J. Tracy

Papers

A 1-Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects

Characterization of sputtered barium strontium titanate and strontium titanate-thin films

Method of fabricating GMR devices

Handbook of multilevel metallization for integrated circuits : materials, technology, and applications

A low power 1 Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects