A switch, switched architecture and process for transferring data through an FCAL switch is disclosed. The switch uses multiple switch control circuits each coupled to one FCAL network and all connected to a crossbar switch. The switch control circuits are coupled together by a protocol bus for coordination purposes. Local conversations can occur on each FCAL loop and crossing conversations through the switch can occur concurrently. The OPN primitive is used to establish the connection before any data is transferred thereby eliminating the need for buffer memory in the switch control circuits. The destination address of each OPN is used to address a lookup table in each switch control circuit to determine if the destination node is local. If not, the destination is looked up and a connection request made on the protocol bus. If the remote port is not busy, it sends a reply which causes both ports to establish a data path through the backplane crossbar switch.

Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost

A data storage system has metadata server machines, content server machines arranged in groups where each group has a respective one or more of the content server machines, and a system interconnect to which the metadata and content server machines are communicatively coupled. A distributed file system is to be executed in the metadata server machines, the content server machines, and the client machine, to hide complexity of the system from a number of client machine users. The content server machines store slices of the files at locations indicated by the metadata. Other embodiments are also described and claimed.

Data storage system

Aspects of the invention may comprise receiving an incoming TCP packet at a TEEC (270) and processing at least a portion of the incoming packet once by the TEEC (270) without having to do any reassembly and/or retransmission by the TEEC (270). At least a portion of the incoming TCP packet may be buffered in at least one internal elastic buffer (280,290) of the TEEC (270). The internal elastic buffer (280,290) may comprise a receive internal elastic buffer (290) and/or a transmit internal elastic buffer (280). Accordingly, at least a portion of the incoming TCP packet may be buffered in the receive internal elastic buffer (290). At least a portion of the processed incoming packet may be placed in a portion of a host memory (230) for processing by a host processor or CPU (210). Furthermore, at least a portion of the processed incoming TCP packet may be DMA transferred to a portion of the host memory (230).

System and method for TCP offload

Systems and methods for network interfacing may include a communication data center with a first tier, a second tier and a third tier. The first tier may include a first server with a first single integrated convergent network controller chip. The second server may include a second server with a second single integrated convergent network controller chip. The third tier may include a third server with a third single integrated convergent network controller chip. The second server may be coupled to the first server via a single fabric with a single connector. The third server may be coupled to the second server via the single fabric with the single connector. The respective first, second and third server, each processes a plurality of different traffic types concurrently via the respective first, second and third single integrated convergent network chip over the single fabric that is coupled to the single connector.

System and method for network interfacing

Aspects of the invention may provide TCP offload, which may include acquiring TCP connection variables from a host and managing at least one TCP connection using the acquired TCP connection variables. At least a portion of the acquired TCP connection variables may be updated and at least some of the updated TCP connection variables may be transferred back to the host. In an aspect of the invention, the TCP connection variables may be variables that are independent of bandwidth delay product. At least a portion of the updated TCP connection variables may be utilized by the host to process the TCP connection or another TCP connection. The host may push the variables onto the stack and the TOE may pull the variables from the stack. Also, updated TCP connection variables may be pushed on the stack by the TOE and pulled from the stack by the host.

System and method for TCP/IP offload independent of bandwidth delay product

A data transfer system comprising a first bus interface, a second bus interface, a first-in-first-out memory, a controller and a message unit. The message unit is operable to queue a plurality of data transfer request messages from the first bus interface and the second bus interface. The controller is operable to process each data transfer request message and transfer data between the first bus interface, the first-in-first-out memory and the second bus interface. The controller is configured to calculate error detection codes (EDCs) and chain EDC values.

Direct memory access controller system with message-based programming

A data transfer system comprising a first bus interface (120), a second bus interface (106), a first-in-first-out memory (105A-105N), a controller (102) and a message unit (108). The message unit (108) is operable to queue a plurality of data transfer request messages from the first bus interface (120) and the second bus interface (106). The controller (102) is operable to process each data transfer request message and transfer data between the first bus interface (120), the first-in-first-out memory (105A-105N) and the second bus interface (106). The controller (102) is configured to calculate error detection codes (EDCs) and chain EDC values.

Direct memory access controller system

A system for enabling input/out virtualization for a device is disclosed. In one embodiment, the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.

John Leland Wood

Papers

Direct memory access controller system with message-based programming

Direct memory access controller system

Inline PCI-IOV Adapter