Patent
Direct memory access controller system with message-based programming
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TLDR
In this paper, a data transfer system comprising a first bus interface, a second bus interface and a first-in-first-out memory, a controller and a message unit is presented.Abstract:
A data transfer system comprising a first bus interface, a second bus interface, a first-in-first-out memory, a controller and a message unit. The message unit is operable to queue a plurality of data transfer request messages from the first bus interface and the second bus interface. The controller is operable to process each data transfer request message and transfer data between the first bus interface, the first-in-first-out memory and the second bus interface. The controller is configured to calculate error detection codes (EDCs) and chain EDC values.read more
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References
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Home automation system
TL;DR: A home automation system comprises a number of sub-systems for controlling various aspects of a house, such as security, HVAC, lighting control, and entertainment, which are connected through a host interface to a plurality of nodes.
Proceedings ArticleDOI
Concurrency, latency, or system overhead: which has the largest impact on uniprocessor DRAM-system performance?
Vinodh Cuppu,Bruce Jacob +1 more
TL;DR: This paper characterizes the sources of overhead in high-performance DRAM systems and investigates the most effective ways to reduce a system's exposure to performance loss.
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TL;DR: In this article, the fill or empty level of a FIFO is detected and compared to a first request level for the direct memory access controller or the coprocessor.
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