Process gas discharged from a bypass pipe to a gas exhaust system can be prevented from diffusing back to the inside of a process chamber without having to install a dedicated vacuum pump at the downstream side of the bypass pipe. The substrate processing apparatus includes a process chamber accommodating a substrate, a gas supply system supplying process gas from a process gas source to the process chamber for processing the substrate, a gas exhaust system configured to exhaust the process chamber, two or more vacuum pumps installed in series at the gas exhaust system, and a bypass pipe connected between the gas supply system and the gas exhaust system. The most upstream one of the vacuum pumps is a mechanical booster pump, and the bypass pipe is connected between the mechanical booster pump and the rest vacuum pumps located at a downstream side of the mechanical booster pump.

Substrate Processing Apparatus

A tray for a dry etching apparatus includes substrate accommodation holes penetrating a thickness direction and a substrate support portion supporting an outer peripheral edge portion of a lower surface of a substrate. An upper portion includes a tray support surface supporting a lower surface of the tray, substrate placement portions on each of which a lower surface of the substrate to be placed, and a concave portion for accommodating the substrate support portion. A dc voltage applying mechanism applies a dc voltage to an electrostatic attraction electrode. A heat conduction gas supply mechanism supplies a heat conduction gas between the substrate and substrate placement portion. During carrying of the substrate, the outer peripheral edge of the lower surface of the substrate is supported by the substrate accommodation hole. During processing of the substrate, the substrate support portion is accommodated in the concave portion.

Plasma processing apparatus and plasma processing method

This invention relates to methods for treatment of semiconductor substrates and in particular a method of etching a trench in a semiconductor substrate in a reactor chamber using alternatively reactive ion etching and depositing a passivation layer by chemical vapour deposition, wherein one or more of the following parameters: gas flow rates, chamber pressure, plasma power, substrate bias, etch rate, deposition rate, cycle time and etching/deposition ratio vary with time.

Method of surface treatment of semiconductor substrates

Substrate processing systems are described that have a capacitively coupled plasma (CCP) unit positioned inside a process chamber. The CCP unit may include a plasma excitation region formed between a first electrode and a second electrode. The first electrode may include a first plurality of openings to permit a first gas to enter the plasma excitation region, and the second electrode may include a second plurality of openings to permit an activated gas to exit the plasma excitation region. The system may further include a gas inlet for supplying the first gas to the first electrode of the CCP unit, and a pedestal that is operable to support a substrate. The pedestal is positioned below a gas reaction region into which the activated gas travels from the CCP unit.

Semiconductor processing system and methods using capacitively coupled plasma

An exemplary system may include a chamber configured to contain a semiconductor substrate in a processing region of the chamber. The system may include a first remote plasma unit fluidly coupled with a first access of the chamber and configured to deliver a first precursor into the chamber through the first access. The system may still further include a second remote plasma unit fluidly coupled with a second access of the chamber and configured to deliver a second precursor into the chamber through the second access. The first and second access may be fluidly coupled with a mixing region of the chamber that is separate from and fluidly coupled with the processing region of the chamber. The mixing region may be configured to allow the first and second precursors to interact with each other externally from the processing region of the chamber.

Semiconductor processing systems having multiple plasma configurations

A wafer lift assembly including an RF shunt is provided. An insulating rim is connected to a powered lift cylinder via a conductive screw. The head of the screw is recessed below a top surface of the rim. A cover is arranged over top of the rim and screw. The RF shunt is a layer of conductive material arranged between the rim and the cover.

Wafer lift assembly

An improved reactive ion plasma etching apparatus having an improved electrode, for holding the product, such as a semiconductor wafer, to be etched, provided with a plurality of apertures into which different tailored product holders are inserted so as to alter the plasma over each holder and provide more uniform etching of the product in the holder regardless of its position on the electrode.

RF Coupling techniques

A semiconductor wafer including a plurality of pits in the semiconductor wafer. The pits are arranged in an information-providing pattern and are readable after completion of processing on the wafer.

Wafer identification mark

Q A reactive ion plasma etching apparatus having an electrode (12), for holding the product, such as a semiconductor wafer (33, 53), to be etched, provided with a plurality of apertures (15, 15a, 15b) into which different tailored product holders are inserted so as to alter the plasma over each holder and provide more uniform etching of the product in the holder regardless of its position on the electrode (12). The holders, like holders (30) and (51), have preferably a recess or a mesa for supporting the wafers.

John W. Lewis

Papers

Wafer lift assembly

RF Coupling techniques

Wafer identification mark

Plasma etching apparatus