An apparatus and method for distracting, in a given direction, and supporting two tissue surfaces. A plurality of wafers are consecutively inserted between the two tissue surfaces to create a column of wafers. The column of wafers is oriented between the tissue surfaces so as to expand in the given direction as the wafers are consecutively added to the column.

Tissue distraction device

A system and method for providing a digital real-time voltage droop detection and subsequent voltage droop reduction. A scheduler within a reservation station may store a weight value for each instruction corresponding to node capacitance switching activity for the instruction derived from pre-silicon power modeling analysis. For instructions picked with available source data, the corresponding weight values are summed together to produce a local current consumption value and this value is summed with any existing global current consumption values from corresponding schedulers of other processor cores yielding an activity event. The activity event is stored. Hashing functions within the scheduler are used to determine both a recent and an old activity average using the calculated activity event and stored older activity events. Instruction issue throttling occurs if either a difference between the old activity average and the recent activity average exceed a first threshold or the recent activity average exceeds a second threshold.

Voltage droop mitigation through instruction issue throttling

A system and method for efficient power transfer on a die. A semiconductor chip comprises on a die two or more computation units (CUs) utilizing at least two different voltage regulators and a power manager. The power manager reallocates power credits across the die when it detects an activity level of a given CU is below a given threshold. In response to receiving a corresponding number of donated power credits, each of the one or more selected CUs maintains a high activity level with a high performance P-state. When a corresponding workload increases, each CU maintains operation and an average power consumption corresponding to the high performance P-state by alternating between at least two different operational voltages. When the operational voltage drops during the alternation, the current drawn by the particular CU may exceed a given current limit. The power manager detects this current limit is exceeded and accordingly reallocates the power credits across the die.

Managing current and power in a computing system

A system and method for real-time power estimation. A core may be divided into units. Each unit is simulated to achieve a real power consumption characterization. The power consumption is sampled. Statistical analysis is performed that assumes the core has node capacitance switching behavior that is approximated by a stationary random process with a Poisson distribution. The statistical analysis determines the number of samples to take during a sample interval. The operational frequency, sample interval, and number of samples are used to determine the number of signals to sample. Signals are chosen that have a high correlation with the node capacitance switching behavior, such as clock enable signals on the last stage of a clock distribution system. Weights with tuned values are assigned to each sampled signal. Sampling occurs during every predetermined number of clock cycles. The weights of asserted sampled signals are summed in order to determine a repeatable power estimation value.

Sampling chip activity for real time power estimation

A flip-flop (10) includes a charge storage area (22) that stores a logic voltage indicating a logic state of the flip-flop (10), a first transistor (20a) having a source or drain connected to a clock generating circuit (40), a second transistor (20b) having a source or drain connected to the clock signal generating circuit (40), a clock signal generated by the clock signal generating circuit (40) that is ramped or sinusoidal, and a latching circuit (18) that latches a latch voltage value based on voltages at the first transistor (20a) and the second transistor (20b). The charge storage area (22) supplies a first voltage representing a state of the storage voltage to a gate of the first transistor (20a) and supplies a second voltage to a gate of the second transistor (20b).

Low-power cmos flip-flop

A flip-flop circuit includes a differential stage coupled to a transparent latch. Respective sides of the differential stage, referred to as the “output side” and the “reference side,” are precharged high during a precharge phase. During an evaluation phase, the state of a data input signal is sensed. Depending upon the state of the data input signal, either the output side or the reference side is discharged. Also, during the evaluation phase, the transparent latch is enabled, and thereby samples and stores an output signal from the output side of the differential stage. Upon initiation of the next precharge phase, the transparent latch is quickly disabled (i.e., is placed in an opaque state), and retains its present state. Since only a single side of the differential stage is used to drive the transparent latch, the differential stage may advantageously be implemented in an asymmetric fashion. In yet an additional embodiment, complex logic may be added to the differential stage of the flip-flop circuit.

John Yong

Papers

Low-power flip-flop circuit employing an asymmetric differential stage