Kai Hwang and Zhiwei Xu  McGraw-Hill, Boston, 1998, 802 pp. ISBN 0-07-031798-4, $97.30 This text is an in depth introduction to the concepts of Parallel Computing. Designed for use in university level computer science courses, the text covers scalable architecture and parallel programming of symmetric muli-processors, clusters of workstations, massively parallel processors, and Internet-based metacomputing platforms. Hwang and Xu give an excellent overview in these topics while keeping the text easily comprehensible. The text is organized into four parts. Part I covers scalability and clustering. Part II deals with the technology used to construct a parallel system. Part III pertains to the architecture of scalable systems. Finally, Part IV presents methods of parallel programming on various platforms and languages. The first chapter presents different models on scalability as divided into resources, applications, and technology. It defines three abstract models (PRAM, BSP, and phase parallel models) and five physical models (PVP, SMP, MPP, COW, and MPP systems). Chapter 2 introduces the ideas behind parallel programming including processes, tasks, threads and environments. Chapter 3 introduces performance issues and metrics. As an introduction to Part II, Chapter 4 introduces the history of microprocessor types and their applications in the architectures of current systems. Chapter 5 deals with the issues of distributed memory. It discusses several models such as UMA, NORMA, CC-NUMA, COMA, and DSM. Chapter 6 presents gigabit networks, switched interconnects, and other various high-speed networking architectures to construct clusters. Chapter 7 discusses the overheads created by parallel computing, such as threads, synchronization, and efficient communication between nodes. Part III, Chapter 8, 9 and 11, give comparisons between various types of scalable systems (SMP, CC-NUMA, Clusters, and MPP). The comparisons are based on hardware architecture, the system software, and special features that make each system unique. Chapter 10 compares various research and commercial clusters with an in depth study of the Berkeley NOW, IBM SP2, and Digital TruCluster systems. Chapter 12 introduces the concepts of Part IV with details into parallel programming paradigms. Chapter 13 discusses communications between the processors using message passing programming (such as MPI and PVM libraries). Chapter 14 studies the data parallel approach with an emphasis in Fortran 90 and HPF. With attention to detail through examples, Hwang and Xu have created a well-written introduction to Parallel Computing. The authors are distinguished for their contributions in this field. This text is based on cutting-edge research, providing the current theories that are in use in industry today. Bin Cong, Shawn Morrison and Michael Yorg, Department of Computer Science  California Polytechnic State University at San Luis Obispo

Scalable Parallel Computing: Technology, Architecture, Programming

Recent technological advances have greatly improved the performance and features of embedded systems. With the number of just mobile devices now reaching nearly equal to the population of Earth, embedded systems have truly become ubiquitous. These trends, however, have also made the task of managing their power consumption extremely challenging. In recent years, several techniques have been proposed to address this issue. In this paper, we survey the techniques for managing power consumption of embedded systems. We discuss the need of power management and provide a classification of the techniques on several important parameters to highlight their similarities and differences. This paper is intended to help the researchers and application-developers in gaining insights into the working of power management techniques and designing even more efficient high-performance embedded systems of tomorrow.

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A survey of techniques for improving energy efficiency in embedded computing systems

https://hal.archives-ouvertes.fr/hal-01103026/document

A Survey of Architectural Techniques For Improving Cache Power Efficiency

As the number of cores on a chip increases and key applications become even more data-intensive, memory systems in modern processors have to deal with increasingly large amount of data. In face of such challenges, data compression presents as a promising approach to increase effective memory system capacity and also provide performance and energy advantages. This paper presents a survey of techniques for using compression in cache and main memory systems. It also classifies the techniques based on key parameters to highlight their similarities and differences. It discusses compression in CPUs and GPUs, conventional and non-volatile memory (NVM) systems, and 2D and 3D memory systems. We hope that this survey will help the researchers in gaining insight into the potential role of compression approach in memory components of future extreme-scale systems.

A Survey Of Architectural Approaches for Data Compression in Cache and Main Memory Systems

Parallel Global Optimization Algorithms (PGOA) provide an efficient way of dealing with hard optimization problems. One method of parallelization of GOAs that is frequently applied and commonly found in the contemporary literature is the so-called Island Model (IM). In this paper, we analyze the impact of the migration topology on the performance of a PGOA which uses the Island Model. In particular we consider parallel Differential Evolution and Simulated Annealing with Adaptive Neighborhood and draw first conclusions that emerge from the conducted experiments.

On the impact of the migration topology on the Island Model

Design and implementation of Performance Analysis Unit (PAU) for AXI-based multi-core System on Chip (SOC)

Adaptive-Classification CLOCK: Page replacement policy based on read/write access pattern for hybrid DRAM and PCM main memory

Compressed tag architecture for low-power embedded cache systems

As the physical gate-count in System-On-Chip (SOC) system increases and system design complexity grows steadily, it becomes more and more difficult to achieve good resource utilization by assigning each task to certain hardware IP and tracing the execution patterns of each task efficiently. Therefore, the performance monitoring feature is getting more and more important to provide the ease of system monitoring and performance debugging. In this paper, we present a performance monitoring unit (PMU) for the AMBA Advanced eXtensible Interface (AXI) bus. The PMU has capability to measure major performance metrics, such as bus latency for the specific master requests and amount of memory traffic for specific durations. It can also measure the contention of the bus masters and slaves in the SOC. We present the distributor and the synchronization method to use multiple performance counting units as well. The performance monitoring unit has been verified in the platform FPGA board with 9 by 4 AXI interconnect configuration. These monitoring features can give the insight to system design architect by helping to find and analyze the performance bottleneck of target system.

Performance monitor unit design for an AXI-based multi-core SoC platform

In multiprocessor systems, interconnection network design is critical for overall system performance. Popular interconnection networks, which are generally considered, are meshes, rings, and hierarchical rings. In this paper, we propose (')Torus Ring('), which is a modified version of hierarchical ring. Torus Ring has the same complexity as the hierarchical rings, but the only difference is the way it connects the local rings. It has an advantage over the hierarchical rings when the destination of a packet is the neighbor local ring in the reverse direction. Though the average number of hops in Torus Ring is equal to that of the hierarchical rings when assuming the uniform distribution of each transaction, the benefits of the number of hops are expected to be larger because of the spatial locality in the real environment of parallel programming. In the simulation results, latencies in the interconnection network are reduced by up to 19, and the execution times are reduced by up to 10.

Jong Wook Kwak

Papers

Design and implementation of Performance Analysis Unit (PAU) for AXI-based multi-core System on Chip (SOC)

Adaptive-Classification CLOCK: Page replacement policy based on read/write access pattern for hybrid DRAM and PCM main memory

Compressed tag architecture for low-power embedded cache systems

Performance monitor unit design for an AXI-based multi-core SoC platform

Torus Ring : Improving Performance of Interconnection Networks by Modifying Hierarchical Ring