In recent years, formal methods have emerged as an alternative approach to ensuring the quality and correctness of hardware designs, overcoming some of the limitations of traditional validation techniques such as simulation and testing.There are two main aspects to the application of formal methods in a design process: the formal framework used to specify desired properties of a design and the verification techniques and tools used to reason about the relationship between a specification and a corresponding implementation. We survey a variety of frameworks and techniques proposed in the literature and applied to actual designs. The specification frameworks we describe include temporal logics, predicate logic, abstraction and refinement, as well as containment between o-regular languages. The verification techniques presented include model checking, automata-theoretic techniques, automated theorem proving, and approaches that integrate the above methods.In order to provide insight into the scope and limitations of currently available techniques, we present a selection of case studies where formal methods were applied to industrial-scale designs, such as microprocessors, floating-point hardware, protocols, memory subsystems, and communications hardware.

Formal verification in hardware design: a survey

From the Publisher:
This book provides an introduction to the foundations of this interdisciplinary research area, emphasizing its applications in computer aided circuit design

Algorithms and data structures in VLSI design

RuleBase is a formal verification tool, developed by the IBM Haifa Research Laboratory. It is the result of three years of experience in practical formal verification of hardware which, we believe, has been a key factor in bringing the tool to its current level of maturity. We present the tool, including several unique features, and summarize our usage experience.

/pdf/rulebase-an-industry-oriented-formal-verification-tool-5emuvyln1s.pdf

RuleBase: an industry-oriented formal verification tool

Traditionally, research on model-driven engineering (MDE) has mainly focused on the use of models at the design, implementation, and verification stages of development. This work has produced relatively mature techniques and tools that are currently being used in industry and academia. However, software models also have the potential to be used at runtime, to monitor and verify particular aspects of runtime behavior, and to implement self-* capabilities (e.g., adaptation technologies used in self-healing, self-managing, self-optimizing systems). A key benefit of using models at runtime is that they can provide a richer semantic base for runtime decision-making related to runtime system concerns associated with autonomic and adaptive systems. This book is one of the outcomes of the Dagstuhl Seminar 11481 on models@run.time held in November/December 2011, discussing foundations, techniques, mechanisms, state of the art, research challenges, and applications for the use of runtime models. The book comprises four research roadmaps, written by the original participants of the Dagstuhl Seminar over the course of two years following the seminar, and seven research papers from experts in the area. The roadmap papers provide insights to key features of the use of runtime models and identify the following research challenges: the need for a reference architecture, uncertainty tackled by runtime models, mechanisms for leveraging runtime models for self-adaptive software, and the use of models at runtime to address assurance for self-adaptive systems.

Models@run.time: foundations, applications, and roadmaps

A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers. Some of the checkers may use signals generated by other checkers.

Method for automatically generating checkers for finding functional defects in a description of a circuit

This paper describes how model checking has been integrated into an industrial hardware design process. We present an application oriented specification language for assumption/commitment style properties and an abstraction algorithm that generates an intuitive and efficient representation of synchronous circuits. These approaches are embedded in our Circuit Verification Environment CVE. They are demonstrated on two industrial applications.

/pdf/model-checking-in-industrial-hardware-design-nzo3xt2lmz.pdf

Model Checking in Industrial Hardware Design

This chapter describes the tools used for automatic verification within the FORMAT project. The FORMAT model checker is the core of this tool set. Figure 1.1 gives an overview on the various languages and tools used on the verification path of FORMAT. Following some short explanations on the overview, the remaining sections of this chapter will give an overview of the architecture of the model checker and each of its components.

The FORMAT Model Checker

A framework for several partial provers is created in the form of a hybrid prover in order to compare two technical systems, especially electric circuits, with each other. The hybrid prover controls the partial provers. The comparison is terminated as soon as a partial prover can determine a result. Said result is used to verify the technical system.

Method and device for comparing technical systems with each other

This chapter presents a summary of the application results obtained by using automatic verification tools in practice. Therefore a summary of the design and verification methodology and a walk through several different applications, which have been treated with formal verifications tools at several different sites of the Siemens AG, is given. For each application we describe the basic functionality and how formal verification technique was used during the design process.

Siemens Industrial Experience

Im Rahmen eines Model Checkings wird versucht, eine Eigenschaft an einem technischen System nachzuweisen. Dazu wird ein Vergleich durchgefuhrt, bei dem mehrere Vergleichsverfahren derart zu koordinieren sind, das der Vergleich zu einem Ergebnis fuhrt. Insbesondere ist der Vergleich beendet, sobald ein Vergleichsverfahren den Nachweis erbringt, das die Eigenschaft in dem System vorliegt bzw. das die dort Eigenschaft nicht enthalten ist.

Jörg Lohse

Papers

Model Checking in Industrial Hardware Design

The FORMAT Model Checker

Method and device for comparing technical systems with each other

Siemens Industrial Experience

Verfahren und anordnung zum vergleich einer ersten eigenschaft mit vorgegebenen eigenschaften eines technischen systems