Showing papers by "José Monteiro published in 1999"

Assignment and reordering of incompletely specified pattern sequences targetting minimum power dissipation

Abstract: For a significant number of electronic systems used in safety-critical applications circuit testing is performed periodically. For these systems, power dissipation due to Built-in Self Test (BIST) can represent a significant percentage of the overall power dissipation. One approach to minimize power consumption in these systems consists of test pattern sequence reordering. Moreover a key observation is that test patterns are in general expected to exhibit don't cares, which can naturally be exploited during test pattern sequence reordering. In this paper we develop an optimization model and describe an efficient algorithm for reordering pattern sequences in the presence of don't cares. Preliminary experimental results amply confirm that the resulting power savings due to pattern sequence reordering using don't cares can be significant.

Power optimization using dynamic power management

Abstract: Power dissipation has recently emerged as one the most critical design constraints. A wide range of techniques has already been proposed for the optimization of logic circuits for low power. Power management methods are among the most effective techniques for power reduction. These methods detect periods of time during which parts of the circuit are not doing useful work and shut them down by either turning off the power supply or the clock signal. Several methods have been presented that perform shut-down on a clock-cycle base. Depending on the input conditions at the beginning of a clock-cycle, the clock driving some of the registers in the circuit can be inhibited, thus reducing the switching activity in the fanout of those registers. These techniques are referred to as data-dependent or dynamic power management techniques. In this tutorial we describe some of the most representative data-dependent power management techniques that have recently been proposed, namely: precomputation, guarded evaluation, gated-clock finite state machines (FSM)'s and FSM decomposition. Each of these techniques uses a different approach to identify the input conditions for which the circuit (or part of) can be disabled. These techniques are put into perspective and recent results are discussed.

A probabilistic approach for RT-level power modeling

Abstract: We propose a method for register-transfer level (RTL) power modeling. The switched capacitance and switching probability of each output of a functional module are modeled by formulas that are a function of the module's inputs probabilities. These formulas are computed beforehand for each module using the polynomial simulation scheme, and stored in the module library. The switched capacitance (and thus power) for each instance of a module in the circuit can then be efficiently evaluated for its specific input probabilities. The switching probabilities at the outputs of each module can be computed in a similar manner, thus providing a means of propagating the switching probabilities through the circuit described at the RT level. We provide a set of experimental results that show that this method provides estimates close to the logic-level estimates, but is orders of magnitude faster.

Integrating Dynamic Power Management in the Design Flow

Abstract: Power dissipation has recently emerged as one of the most critical design constraints. A wide range of techniques has already been proposed for the optimization of logic circuits for low power. Power management methods are among the most effective techniques for power reduction. These methods detect periods of time during which parts of the circuit are not doing useful work and shut them down by either turning off the power supply or the clock signal.