Showing papers by "José Monteiro published in 2008"

Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications

Abstract: The main contribution of this paper is an exact common subexpression elimination algorithm for the optimum sharing of partial terms in multiple constant multiplications (MCMs). We model this problem as a Boolean network that covers all possible partial terms that may be used to generate the set of coefficients in the MCM instance. We cast this problem into a 0-1 integer linear programming (ILP) by requiring that the single output of this network is asserted while minimizing the number of gates representing operations in the MCM implementation that evaluate to one. A satisfiability (SAT)-based 0-1 ILP solver is used to obtain the exact solution. We argue that for many real problems, the size of the problem is within the capabilities of current SAT solvers. Because performance is often a primary design parameter, we describe how this algorithm can be modified to target the minimum area solution under a user-specified delay constraint. Additionally, we propose an approximate algorithm based on the exact approach with extremely competitive results. We have applied these algorithms on the design of digital filters and present a comprehensive set of results that evaluate ours and existing approximation schemes against exact solutions under different number representations and using different SAT solvers.

Efficient dedicated multiplication blocks for 2’s complement radix-16 and radix-256 array multipliers

Abstract: In this paper, we introduce new dedicated blocks for radix-16 and radix-256 multiplication. These blocks are basic components of the structure of the 2psilas complement radix-2m array multiplier proposed previously in the literature. In the original array multiplier, the blocks that perform the radix-16 multiplication were automatically synthesized from a truth table. The dedicated radix-16 multiplication blocks we propose are themselves composed of a structure of less complex multiplication blocks and resort to efficient Carry Save adders (CSA). This new scheme can be naturally extended for radix-256 multiplication. We present results of area, delay and power consumption for 16, 32 and 64 bit array multipliers using the new dedicated modules. The results show that by using the new dedicated modules, the array multipliers are more efficient in terms of delay and power consumption when compared both against the original array structure and the Modified Booth multiplier.

Computation of the minimal set of paths for observability-based statement coverage

Abstract: Existing coverage-based validation methods guarantee the execution of a certain percentage of the program code under test, however they do not generally verify whether the statements executed have any influence on the program’s output. Motivated by an observability coverage metric for embedded software we propose a coverage-directed path generation method. In this method, a program statement is considered covered not only if it belongs to the executed path, but also if its execution has influence in some output. The paths are generated by finding the longest path in a tree representing the possible execution paths of the program. Generated paths are then validated to check for feasibility. If a feasible path is found, then we determine and mark the statements actually observed using the computed inputs for exercising the path. If unfeasible, we search for the next longest path. If the desired level of coverage was not obtained yet then a new tree is built. This new tree will reflect the coverage obtained so far and also the information gathered when checking the feasibility of previous paths. We present results that demonstrate the effectiveness of this methodology.