Personalization of the e-learning systems according to the learner’s needs and knowledge level presents the key element in a learning process. E-learning systems with personalized recommendations should adapt the learning experience according to the goals of the individual learner. Aiming to facilitate personalization of a learning content, various kinds of techniques can be applied. Collaborative and social tagging techniques could be useful for enhancing recommendation of learning resources. In this paper, we analyze the suitability of different techniques for applying tag-based recommendations in e-learning environments. The most appropriate model ranking, based on tensor factorization technique, has been modified to gain the most efficient recommendation results. We propose reducing tag space with clustering technique based on learning style model, in order to improve execution time and decrease memory requirements, while preserving the quality of the recommendations. Such reduced model for providing tag-based recommendations has been used and evaluated in a programming tutoring system.

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Enhancing e-learning systems with personalized recommendation based on collaborative tagging techniques

A stable and efficient anti-collision protocol is very important for tags identification in many radio frequency identification (RFID) system such as flow productions and automatic controls. In this paper, we introduce an efficient anti-collision protocol named collision tree protocol (CT) and analyze the stability of it in detail. Both theoretical results and experimental results indicate that the performance of CT is only dependent on the number of tags to be identified and not influenced by the distribution of tag IDs and other factors, and the average performance of CT for one-tag identification converges to a constant. According to the definition of the stability of an anti-collision protocol, CT is a stable anti-collision protocol for RFID tag identification. The stability proposed in this paper provides a new performance metric for evaluating the performance of different anti-collision protocols for RFID tag identification. As a stable protocol, the time delay and the power consumption for one-tag identification of CT tend to be constant. Therefore, CT can be applied to various tags identification systems and especially suited to the RFID systems in which both the time delay and the power consumption for tags (or objects) identification are required to be limited and stable.

Stability Analysis of an Efficient Anti-Collision Protocol for RFID Tag Identification

An automated, FPGA-based reconfigurable, low-power RFID tag

A comparison of glucose oxidase and aldose dehydrogenase as mediated anodes in printed glucose/oxygen enzymatic fuel cells using ABTS/laccase cathodes.

This paper describes a low-jitter delay-locked loop (DLL)-based clock generator for dynamic frequency scaling in the extendable instruction set computing (EISC) processor. The DLL-based clock generator provides the system clock with frequencies of 0.5× to 8× of the reference clock, according to the workload of the EISC processor. The proposed analog self-calibration method and a phase detector with an auxiliary charge pump can effectively reduce the delay mismatch between delay cells in the voltage-controlled delay line and the static phase offset due to the current mismatch in the charge pump, respectively. The self-calibrated output waveform exhibits 9.7 ps of RMS jitter and 73.7 ps of peak-to-peak jitter at 120 MHz. The prototype clock generator implemented in a 0.18-μm CMOS process occupies an active area of 0.27 mm2 and consumes 15.56 mA.

A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor

Multiprocessor Systems on Chips (MPSoCs) have become a popular architectural technique to increase performance. However, MPSoCs may lead to undesirable power consumption characteristics for computing systems that have strict power budgets, such as PDAs, mobile phones, and notebook computers. This paper presents the super-complex instruction-set computing (SuperCISC) Embedded Processor Architecture and, in particular, investigates performance and power consumption of this device compared to traditional processor architecture-based execution. SuperCISC is a heterogeneous, multicore processor architecture designed to exceed performance of traditional embedded processors while maintaining a reduced power budget compared to low-power embedded processors. At the heart of the SuperCISC processor is a multicore VLIW (Very Large Instruction Word) containing several homogeneous execution cores/functional units. In addition, complex and heterogeneous combinational hardware function cores are tightly integrated to the core VLIW engine providing an opportunity for improved performance and reduced energy consumption. Our SuperCISC processor core has been synthesized for both a 90-nm Stratix II Field Programmable Gate Aray (FPGA) and a 160-nm standard cell Application-Specific Integrated Circuit (ASIC) fabrication process from OKI, each operating at approximately 167 MHz for the VLIW core. We examine several reasons for speedup and power improvement through the SuperCISC architecture, including predicated control flow, cycle compression, and a reduction in arithmetic power consumption, which we call power compression. Finally, testing our SuperCISC processor with multimedia and signal-processing benchmarks, we show how the SuperCISC processor can provide performance improvements ranging from 7X to 160X with an average of 60X, while also providing orders of magnitude of power improvements for the computational kernels. The power improvements for our benchmark kernels range from just over 40X to over 400X, with an average savings exceeding 130X. By combining these power and performance improvements, our total energy improvements all exceed 1000X. As these savings are limited to the computational kernels of the applications, which often consume approximately 90p of the execution time, we expect our savings to approach the ideal application improvement of 10X.

Reducing power while increasing performance with supercisc

This paper describes an ultra low power active RFID tag and its automated design flow. RFID primitives to be supported by the tag are enumerated with RFID macros and the behavior of each primitive is specified using ANSI-C within the template to automatically generate the tag controller. Two power saving components, a passive transceiver/burst switch and a smart buffer, are presented to save power and increase tag lifetime. Based on a test program, the processors required 183, 43, and 19 /spl mu/J per transaction for StrongARM, XScale, and EISC processors, respectively. Three hardware controllers using a Fusion FPGA, Coolrunner II CPLD, and ASIC required 13 nJ, 1.3 nJ, and 0.07 nJ per transaction.

An automated, reconfigurable, low-power RFID tag

Current Radio Frequency Identification (RFID) systems generally have long design times and low tolerance to changes in specification. This paper describes a field programmable, low-power active RFID tag, and its associated specification and automated design flow. RFID primitives to be supported by the tag are enumerated with RFID macros, or assembly-like descriptions of the tag operations. From these, the RFID preprocessor generates templates automatically. The behavior of each RFID primitive is specified using ANSI C in the template. The resulting file is compiled by the RFID compiler. A smart buffer sits between the transceiver and the tag controller, to detect whether incoming packets are intended for the tag. By doing so, the main controller may remain powered down to reduce power consumption. Two System-on-a-Chip implementation strategies are presented. First, a microprocessor based system for which a C program is automatically generated. The second includes a block of low-power FPGA logic. The user supplied RFID logic in ANSI-C is automatically converted into combinational VHDL by the RFID compiler. Based on a test program, the processors required 183, 43, and 19 ?J per transaction for StrongARM, XScale, and EISC processors, respectively. By replacing the processor with a Coolrunner II, the controller can be reduced to 1.11 nJ per transaction.

Josh Fazekas

Papers

Reducing power while increasing performance with supercisc

An automated, reconfigurable, low-power RFID tag

A Field Programmable RFID Tag and Associated Design Flow