Joshua B. Fryman

TL;DR: An initial evaluation of Runnemede is presented that shows the design process for the on-chip network, demonstrates 2-4x improvements in memory energy from explicit control of on- chip memory, and illustrates the impact of hardware-software co-design on the energy consumption of a synthetic aperture radar algorithm on the architecture.

TL;DR: In this article, a multi-core processor having cores each associated with a cache memory, can operate such that when a first core is to access data owned by a second core, responsive to a request from the first core, cache coherency state information associated with the cache line is not updated.

TL;DR: This paper provides initial performance estimations, projecting that a PIUMA node will outperform a conventional compute node by one to two orders of magnitude, and continues to scale across multiple nodes, which is a challenge in conventional multinode setups.

TL;DR: This paper analyzes multiple graph applications on current multi and many-core processors, and provides conclusions and recommendations for future designs to provide more scalable parallelism and to exploit the potential of many- core architectures with high-bandwidth memory.

TL;DR: In this paper, a method for decoding in a processor core and dynamically handling the instruction with one of multiple behaviors based on whether contention is predicted is described, if no contention is detected, the instruction is executed in the core, and if contention is inferred, data associated with the instruction are marshaled and sent to a selected remote agent for execution.