A frequency synthesiser receives a sequence of digital pulses (Fq) and provides as an output a lower frequency consisting of a slightly irregular sequence of pulses. The synthesiser divides the received frequency by a non-integral value by arranging for a variable frequency divider (5) to divide the received sequence of pulses and by periodically removing the received pulses prior to division so as to in effect, temporarily alter the division ratio.

A method of synthesizing an output frequency and circuit arrangement therefor

A reference source of digital pulses of a first frequency f 1 is coupled to the input of a frequency synthesizer which is capable of providing a second frequency f 2 output signal. The second frequency is related to the first frequency by a predetermined, rational fraction (e.g., as f 2 = (M/N)f 1 ). The synthesizer includes a phase control unit comprising an adder by way of which a first number N is added each sample period to a remainder, the sum output of the adder being operated upon modulo a second number M, e.g., by dividing by M and discarding a resultant quotient to obtain a remainder. The remainder, having a value between zero and M-1, is compared to a prefixed signal, illustratively the largest integer in M/2. If the remainder is less than the prefixed signal, a first logic state control signal is provided to a control system; else a second logic state signal is so provided. The alternation between the first and second logic states is such that M pulses of the second frequency occur for every N pulses of the first frequency. Thereby, the second frequency is synthesized responsive to the first.

Phase locked loop frequency synthesizer using digital modulo arithmetic

A counter/divider dividing an input frequency (F1) by 2 q+n +1/2, comprises a first divider by 2 q (30) receiving the signal to divide of a frequency F1 and provides 2 q+1 outputs at the frequency F1/2 q out of phase the ones to the others of 360°/2 q+1 ; a multiplexer (32) having a control terminal (34) and sequentially providng at its output (33) each of said 2 q+1 outputs each time a control signal is applied; and a second divider by 2 n (31) receiving the output (33) of the multiplexer and providing the desired output (34) of the counter/divider, this output being applied to the control terminal of the multiplexer.

Fast counter/divider and its use in a swallower counter

The digital circuit is for receiving a master clock signal at a frequency te f on an input and delivering a rectangular shaped output signal at a lower frequency (M/N)f where M is an integer and N is an even integer greater than M. The circuit comprises an even number N of series connected flip-flops in a ring arrangement, each flip-flop being connected to receive input signals from the preceding flip-flop and from the following flip-flop and to receive a master clock signal on a clock input. The even numbered flip-flops are of a type different from the type of the odd numbered flip-flops. The outputs of the flip-flops each deliver a rectangular pulse signal having a duty ratio equal to 1/N of that of the master clock signal. The pulse signals are applied to a combination logic of OR type giving an output signal combining the outputs of said plurality of flip-flops.

Digital circuit for frequency or pulse rate division

A smooth pulse sequence (SSM) which is a rational fraction (M/N) of an available uniform sequence (SIN) is generated by employing an address generator (10) and a read only memory (ROM 15). Signal representations are stored in the ROM (15) which define the smooth sequence pulse transitions. The address generator (10) is driven by the reference signal and, in turn, generates a sequence of address signals which, when applied to the ROM (15) cause the smooth pulse sequence (SSM) to be read out. The smooth pulse sequence (SSM) is filtered (16) and shaped (17) to obtain a desired uniform pulse sequence (SOUT) which is in synchronism with the reference signal (SIN).

Smooth pulse sequence generator

A reference source of uniformly spaced pulses is coupled to the input of a smooth sequence generator (SSG) which is capable of dividing the reference pulse sequence by any proper, predetermined, rational fraction (e.g., 193/512). The SSG comprises a plurality of routing circuits connected in tandem. Each routing circuit has a first and second output and a control terminal which serves to route a pulse presented at the routing circuit input to either said first or second output. The first output of each routing circuit is connected to the next tandem-connected routing circuit. A feedback connection from the first output of each routing circuit to the control terminal of the preceding routing circuit serves to control the routing of a pulse presented to the input of the latter. A synchronization circuit is coupled to the output of said reference source, via a divider circuit, and to the first output of the last tandem-connected routing circuit. The sync circuit output is delivered to the control terminal of said last routing circuit to constrain (i.e., lock) the frequency, and preferably even the phase, of the SSG source.

Jr. Carl Jerome May

Papers

Smooth sequence generator for fractional division purposes