Fast Fourier Transform

In this article, we survey existing academic and commercial efforts to provide Field-Programmable Gate Array (FPGA) acceleration in datacenters and the cloud. The goal is a critical review of existing systems and a discussion of their evolution from single workstations with PCI-attached FPGAs in the early days of reconfigurable computing to the integration of FPGA farms in large-scale computing infrastructures. From the lessons learned, we discuss the future of FPGAs in datacenters and the cloud and assess the challenges likely to be encountered along the way. The article explores current architectures and discusses scalability and abstractions supported by operating systems, middleware, and virtualization. Hardware and software security becomes critical when infrastructure is shared among tenants with disparate backgrounds. We review the vulnerabilities of current systems and possible attack scenarios and discuss mitigation strategies, some of which impact FPGA architecture and technology. The viability of these architectures for popular applications is reviewed, with a particular focus on deep learning and scientific computing. This work draws from workshop discussions, panel sessions including the participation of experts in the reconfigurable computing field, and private discussions among these experts. These interactions have harmonized the terminology, taxonomy, and the important topics covered in this manuscript.

The Future of FPGA Acceleration in Datacenters and the Cloud

The year 2011 marked an important transition for FPGA high-level synthesis (HLS), as it went from prototyping to deployment. A decade later, in this article, we assess the progress of the deployment of HLS technology and highlight the successes in several application domains, including deep learning, video transcoding, graph processing, and genome sequencing. We also discuss the challenges faced by today’s HLS technology and the opportunities for further research and development, especially in the areas of achieving high clock frequency, coping with complex pragmas and system integration, legacy code transformation, building on open source HLS infrastructures, supporting domain-specific languages, and standardization. It is our hope that this article will inspire more research on FPGA HLS and bring it to a new height.

FPGA HLS Today: Successes, Challenges, and Opportunities

Wireshark-based debugging can be performed on ordinary desktop computers at 1G speeds, but only powerful computers can keep up with 10G. At 100G, this debugging becomes virtually impossible to perform on a single machine.This work presents FFShark, a Fast FPGA implementation of Wireshark. The result is a compact, relatively inexpensive passthrough device that can be inserted into any running 100G network. Packets will travel through FFShark with no interruption and minimal additional latency. A developer can send standard Wireshark filter programs to the FFShark device at any time; packets that satisfy the filter will be copied and sent back to the developer’s workstation over a separate connection.We show that our open source passthrough device has lower latency than commercial 100G switches, and that our design is already capable of handling 400G speeds.

FFShark: A 100G FPGA Implementation of BPF Filtering for Wireshark

FPGA-based SmartNICs offer great potential to significantly improve the performance of high-performance computing and warehouse data processing by tightly coupling support for reconfigurable data-intensive computation with cross-node communication thereby mitigating the von Neumann bottleneck. Existing work however has generally been limited in that it assumes an accelerator model where kernels are offloaded to SmartNICs with most control tasks left to the CPUs. This leads to frequent waiting reduced performance and scaling challenges. In this work we propose a new distributive data-centric computing framework named FCsN for reconfigurable SmartNIC-based systems. Through a lightweight task circulation execution model and its implementation architecture FCsN allows the complete detaching of NN kernel execution control logic system scheduling and network communication to the SmartNICs. This boosts performance by (i) avoiding control dependency with CPUs and (ii) supporting streaming NN kernel execution and network communication at line rate and in a very fine-grained manner. We demonstrate the efficiency and flexibility of FCsN using various types of neural network kernels and applications including deep neural networks (DNN) and graph neural networks (GNN) as these last are both irregular and data intensive they offer an especially robust demonstration. Evaluations using commonly-used neural network models and graph datasets show that a system with FCsN can achieve 10 × speedups over the MPI-based standard CPU baselines

A Framework for Neural Network Inference on FPGA-Centric SmartNICs

Introducing ReCPRI: A Field Re-configurable Protocol for Backhaul Communication in a Radio Access Network

Drivers for accessing storage are complex. In addition to the complexity involved in using the NVMe protocol, navigating filesystems requires multiple serialized storage accesses and data processing between each access. As a result, efforts to create storage drivers for FPGAs, so that FPGAs can directly access storage without help from a CPU, have either failed, require too many resources/time, or remove some of the functionality expected by storage users (such as removing the filesystem) [1], [2].

SHIP: Storage for Hybrid Interconnected Processors

Future telecommunications networks require more throughput and lower latency. The slowdown of Moore’s Law forces one to think beyond traditional CPU servers to satisfy these needs. FPGAs have been shown to provide exceptional throughput and latency, but they currently lack support for many of the orchestration and reconfiguration tools required by telecommunications networks, namely exposing a standard configuration API for SDN applications to control, and having the ability for tools such as Kubernetes to provision and reuse these compute resources.We propose an FPGA Framework for Interactive VNF Environments, or FFIVE for short. We utilize the framework for the creation of FPGA-based containers allowing them to be deployed by Kubernetes and virtually connected via VXLAN. This enables us to migrate the FPGA as needed in the virtual network, allowing for quick image substitution as usage changes. We also enable the use of RESTful APIs to control, reprogram, and manage an FPGA making it usable by SDN applications. Essentially, our framework makes the deployment and management of FPGA-based containers in telecom analogous to their CPU counterparts but with the improved bandwidth, efficiency, and latency provided by FPGAs. Comparing the network stack and chaining of our approach with conventional multi-threaded CPU server implementations, we offer 59-fold to 175-fold throughput increase and a 97.5% reduction of latency for networking and chaining. We are also able to reduce the latency of a real-world firewall VNF by 92.3%.

Juan Camilo Vega

Papers

The Future of FPGA Acceleration in Datacenters and the Cloud

FFShark: A 100G FPGA Implementation of BPF Filtering for Wireshark

Introducing ReCPRI: A Field Re-configurable Protocol for Backhaul Communication in a Radio Access Network

SHIP: Storage for Hybrid Interconnected Processors

A Framework Integrating FPGAs in VNF Networks