R
Russell Tessier
Researcher at University of Massachusetts Amherst
Publications - 159
Citations - 4934
Russell Tessier is an academic researcher from University of Massachusetts Amherst. The author has contributed to research in topics: Field-programmable gate array & Reconfigurable computing. The author has an hindex of 34, co-authored 152 publications receiving 4557 citations. Previous affiliations of Russell Tessier include Yale University & Massachusetts Institute of Technology.
Papers
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Book
FPGA Architecture: Survey and Challenges
TL;DR: This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures.
Journal ArticleDOI
Reconfigurable Computing for Digital Signal Processing: A Survey
Russell Tessier,Wayne Burleson +1 more
TL;DR: A survey of academic research and commercial development in reconfigurable computing for DSP systems over the past fifteen years is presented in this article, with a focus on the application domain of digital signal processing.
Patent
Virtual interconnections for reconfigurable logic systems
TL;DR: In this article, a compilation technique overcomes device pin limitations using virtual interconnections is presented, by intelligently multiplexing each physical wire among multiple logical wires and pipelining these connections at the maximum clocking frequency.
Proceedings ArticleDOI
Virtual wires: overcoming pin limitations in FPGA-based logic emulators
TL;DR: Results from compiling netlists indicate that virtual wires can increase FPGA gate utilization beyond 80 percent without a significant slowdown in emulation speed.
Journal ArticleDOI
Logic emulation with virtual wires
TL;DR: Results, including in-circuit emulation of a SPARC microprocessor, indicate that virtual wires eliminate the need for expensive crossbar technology while increasing FPGA utilization beyond 45% andoretical analysis predicts thatvirtual wires emulation scales with FPN size and average routing distance, while traditional emulation does not.