Fast Fourier Transform

Solitons are waveforms that preserve their shape while propagating, as a result of a balance of dispersion and nonlinearity. Soliton-based data transmission schemes were investigated in the 1980s and showed promise as a way of overcoming the limitations imposed by dispersion of optical fibres. However, these approaches were later abandoned in favour of wavelength-division multiplexing schemes, which are easier to implement and offer improved scalability to higher data rates. Here we show that solitons could make a comeback in optical communications, not as a competitor but as a key element of massively parallel wavelength-division multiplexing. Instead of encoding data on the soliton pulse train itself, we use continuous-wave tones of the associated frequency comb as carriers for communication. Dissipative Kerr solitons (DKSs) (solitons that rely on a double balance of parametric gain and cavity loss, as well as dispersion and nonlinearity) are generated as continuously circulating pulses in an integrated silicon nitride microresonator via four-photon interactions mediated by the Kerr nonlinearity, leading to low-noise, spectrally smooth, broadband optical frequency combs. We use two interleaved DKS frequency combs to transmit a data stream of more than 50 terabits per second on 179 individual optical carriers that span the entire telecommunication C and L bands (centred around infrared telecommunication wavelengths of 1.55 micrometres). We also demonstrate coherent detection of a wavelength-division multiplexing data stream by using a pair of DKS frequency combs-one as a multi-wavelength light source at the transmitter and the other as the corresponding local oscillator at the receiver. This approach exploits the scalability of microresonator-based DKS frequency comb sources for massively parallel optical communications at both the transmitter and the receiver. Our results demonstrate the potential of these sources to replace the arrays of continuous-wave lasers that are currently used in high-speed communications. In combination with advanced spatial multiplexing schemes and highly integrated silicon photonic circuits, DKS frequency combs could bring chip-scale petabit-per-second transceivers into reach.

Microresonator-based solitons for massively parallel coherent optical communications

Optical frequency combs have the potential to revolutionize terabit communications1. Generation of Kerr combs in nonlinear microresonators2 represents a particularly promising option3 enabling line spacings of tens of GHz. However, such combs may exhibit strong phase noise4-6, which has made high-speed data transmission impossible up to now. Here we demonstrate that systematic adjustment of pump conditions for low phase noise4,7-9 enables coherent data transmission with advanced modulation formats that pose stringent requirements on the spectral purity of the comb. In a first experiment, we encode a data stream of 392 Gbit/s on a Kerr comb using quadrature phase shift keying (QPSK) and 16-state quadrature amplitude modulation (16QAM). A second experiment demonstrates feedback-stabilization of the comb and transmission of a 1.44 Tbit/s data stream over up to 300 km. The results show that Kerr combs meet the highly demanding requirements of coherent communications and thus offer an attractive solution towards chip-scale terabit/s transceivers.

/pdf/coherent-terabit-communications-with-microresonator-kerr-vlw55yir8t.pdf

Coherent terabit communications with microresonator Kerr frequency combs.

The paper describes architectural enhancements to Xilinx FPGAs that provide better support for the creation of dynamically reconfigurable designs. These are augmented by a new design methodology that uses pre-routed IP cores for communication between static and dynamic modules and permits static designs to route through regions otherwise reserved for dynamic modules. A new CAD tool flow to automate the methodology is also presented. The new tools initially target the Virtex-II, Virtex-II Pro and Virtex-4 families and are derived from Xilinx's commercial CAD tools

Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs

Over the past decade, optical frequency combs generated by high-Q microresonators, or optical microcombs, which feature compact device footprints, low power consumption, and high repetition rates in broad optical bandwidths, have led to a revolution in a wide range of fields including metrology, telecommunications, radio frequency (RF) photonics, spectroscopy, sensing, and quantum optics. Among these, an application that has attracted great interest is the use of optical microcombs for RF photonics, where they offer enhanced functionalities as well as reduced size and power consumption over other approaches. This paper reviews the recent advances in this emerging field. We provide an overview of the main achievements that have been obtained to date, and highlight the strong potential of optical microcombs for RF photonics applications. We also discuss some of the open challenges and limitations that need to be addressed for practical applications.

RF Photonics: An Optical Microcombs’ Perspective

http://ieeexplore.ieee.org/iel5/6292850/6292851/06293040.pdf

Ultra high speed digital down converter design for Virtex-6 FPGAs

Multicores, being the latest state-of-the-art technology, gain more and more importance in automotive and aerospace systems. This technology will not only be used in infotainment and non-safety-critical applications but will also be introduced in upcoming safety-critical systems. At the moment, various commercial off-the-shelf processors are available that are, however, not built for such applications. In order to ensure correct system behavior, online monitoring can be used for processors targeting infotainment or general purpose applications. The cores and other bus masters within the MPSoC compete for the exclusive use of shared resources like a memory controller. It is of high importance to provide guarantees of usage in such cases, e.g. in terms of access time and rates. For this purpose we present an online monitoring based on a commercial off-the-shelf multicore processor that provides knowledge about the usage of the direct memory access (DMA) controller in terms of accesses and activation sources. Furthermore, with this information, conclusions about the memory controller workload are drawn. The concept is implemented by using Freescale’s i.MX6 Quad platform, which is targeting automotive infotainment. This paper aims to show how such general purpose multicore processors can be partly adapted to provide evidence for safety related systems.

Adapting Commercial Off-The-Shelf Multicore Processors for Safety-Related Automotive Systems Using Online Monitoring

State-of-the-art multi-core reconfigurable processors do not exploit the full potential of simultaneous multi-tasking with run-time adaptive reconfigurable fabric allocation. We propose a novel run-time system for simultaneous multi-tasking in a multi-core reconfigurable processor that adaptively allocates the mixed-grained reconfigurable fabric resource at run time among different tasks considering their performance constraints. Our scheme employs the novel concept of refined task-criticality (based on the functional-block-level performance constraints) considering the computational properties of dependent tasks and their inherent potential for acceleration. Our scheme dynamically compensates the deadline misses at the functional block level. It thereby reduces the potential task-level deadline misses under competing scenarios. With the help of a secure video conferencing application (with 4 dependent tasks of diverse computational properties), we demonstrate that our scheme reduces the deadline misses by (on average) 6x under given performance constraints, when compared to state-of-the-art reconfigurable processors [1, 9, 12].

/pdf/run-time-resource-allocation-for-simultaneous-multi-tasking-4wm1ryozb5.pdf

Run-Time Resource Allocation for Simultaneous Multi-tasking in Multi-core Reconfigurable Processors

This work describes a methodology to model power consumption of logic modules. A detailed mathematical model is presented and incorporated in a tool for translation of models written in VHDL to SystemC. The functionality for implicit power monitoring and estimation is inserted at module translation. The translation further implements an approach to wrap RTL to TLM interfaces so that the translated module can be connected to a system-level simulator. The power analysis is based on a statistical model of the underlying HW structure and an analysis of input data. The flexibility of the C++ syntax is exploited, to integrate the power evaluation technique. The accuracy and speed-up of the approach are illustrated and compared to a conventional power analysis flow using PPR simulation, based on Xilinx technology.

/pdf/modeling-and-implementation-of-a-power-estimation-1wqrr2mgx8.pdf

Modeling and implementation of a power estimation methodology for systemC

Nowadays, the datapaths of modern microprocessors reach their limits by using static instruction sets. A way out of this limitations is a dynamic reconfigurable processor datapath extension achieved by integrating traditional static datapaths with the coarse-grain dynamic reconfigurable XPP-architecture (extreme processing platform). Therefore, a loosely asynchronous coupling mechanism of the corresponding datapath units has been developed and integrated onto a CMOS 0.13 /spl mu/m in standard cell technology from UMC. Here the SPARC compatible LEON processor is used, whereas its static pipelined instruction datapath has been extended to be configured and personalized for specific applications. This allows a various and efficient use, e.g. in streaming application domains like MPEG-4, digital filters, mobile communication modulation, etc. The chosen coupling technique allows asynchronous concurrency of the additionally configured compound instructions, which are integrated into the programming and compilation environment of the LEON processor.

Juergen Becker

Papers

Ultra high speed digital down converter design for Virtex-6 FPGAs

Adapting Commercial Off-The-Shelf Multicore Processors for Safety-Related Automotive Systems Using Online Monitoring

Run-Time Resource Allocation for Simultaneous Multi-tasking in Multi-core Reconfigurable Processors

Modeling and implementation of a power estimation methodology for systemC

Efficient processor instruction set extension by asynchronous reconfigurable datapath integration