Power consumption is forecast by the International Technology Roadmap of Semiconductors (ITRS) to pose long-term technical challenges for the semiconductor industry. The purpose of this paper is threefold: (1) to provide an overview of strategies for powering MEMS via non-regenerative and regenerative power supplies; (2) to review the fundamentals of piezoelectric energy harvesting, along with recent advancements, and (3) to discuss future trends and applications for piezoelectric energy harvesting technology. The paper concludes with a discussion of research needs that are critical for the enhancement of piezoelectric energy harvesting devices.

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Powering MEMS portable devices—a review of non-regenerative and regenerative power supply systems with special emphasis on piezoelectric energy harvesting systems

Based on a Fourier series analysis, an analytic interconnect model is presented which is suitable for periodic signals, such as a clock signal. In this model, the far-end time-domain waveform is approximated by the summation of several sinusoids. Closed-form solutions of the 50% delay and overshoots/undershoots are provided when the fifth and higher order harmonics are ignored. Good accuracy is observed between the model and SPICE simulations. The model is applied to resistance-capacitance-inductance interconnect trees and the computational complexity of the model is linear with the size of the tree and the model order. The tree model is shown to be an effective method to analyze clock distribution networks. The single interconnect model is also extended to coupled multi-interconnect systems to analyze crosstalk noise and a general waveform solution is obtained. It is noted that in addition to the transition time, the period of the aggressor signal also has a significant effect on the crosstalk noise.

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An RLC interconnect model based on fourier analysis

In this paper, we first show that existing net ordering formulations to minimize noise are no longer valid with presence of inductive noise, and shield insertion is needed to minimize inductive noise. We then formulate two simultaneous shield insertion and net ordering (SINO) problems: the optimal SINO/NF problem to find a min-area SINO solution that is free of capacitive and inductive noise, and the optimal SINO/NB problem to find a min-area SINO solution that is free of capacitive noise and is under the given inductive noise bound. We reveal that both optimal SINO problems are NP-hard, and propose effective approximate algorithms for the two problems. Experiments show that our SINO/NB algorithm uses from 15% to 57% fewer shield wires when compared to separated net ordering and shield insertion procedure. Furthermore, under practical noise bounds, the SINO/NB solutions use from 44% to 67% fewer shield wires when compared to SINO/NF solutions, and use 10% to 40% fewer shield wires when compared to the theoretical lower bound for optimal SINO/NF solutions. Additionally, all our algorithms are extremely efficient to finish all examples in a few seconds. To the best of our knowledge, it is the first work that presents an in-depth study on the simultaneous shield insertion and net ordering problem to minimize both capacitive and inductive noise.

Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization

Modern transmission line theory and applications

On-chip interconnect delay and crosstalk noise have become significant bottlenecks in the performance and signal integrity of deep submicrometer VLSI circuits. A crosstalk noise model for both identical and nonidentical coupled resistance-inductance-capacitance (RLC) interconnects is developed based on a decoupling technique exhibiting an average error of 6.8% as compared to SPICE. The crosstalk noise model, together with a proposed concept of effective mutual inductance, is applied to evaluate the effectiveness of the shielding technique

Crosstalk modeling for coupled RLC interconnects with application to shield insertion

With high integration density of today's electronic system and reduced noise margins, maintaining high power integrity becomes more challenging for high performance design. Inserting decoupling capacitors is one important and effective solution to improve the power integrity. The existing decoupling capacitor optimization approaches meet constraints on input impedance. In this paper, we show that impedance metric leads to large overdesign and then develop a noise-driven optimization algorithm for decoupling capacitors in packages for power integrity. We use the simulated annealing algorithm to minimize the total cost of decoupling capacitors under the constraints of a worst case noise bound. The key enabler for efficient optimization is an incremental worst case noise computation based on fast Fourier transform over incremental impedance matrix evaluation. Compared to the existing impedance-based approaches, our algorithm reduces the decoupling capacitor cost by 3times and is also more than 10times faster even with explicit noise computation

/pdf/efficient-in-package-decoupling-capacitor-optimization-for-i-3n6qamurdu.pdf

Efficient In-Package Decoupling Capacitor Optimization for I/O Power Integrity

In this article, we first show that existing net ordering formulations to minimize noise are no longer sufficient with the presence of inductive noise, and shield insertion is needed to minimize inductive noise. Using a Keff model as the figure of merit for inductive coupling, we then formulate two simultaneous shield insertion and net ordering (SINO) problems: the optimal SINO/NF problem to find a minimal area SINO solution that is free of capacitive and inductive noise, and the optimal SINO/NB problem to find a minimal area SINO solution that is free of capacitive noise and is under the given inductive noise bound. We reveal that both optimal SINO problems are NP-hard, and propose effective approximate algorithms for the two problems. Experiments show that our SINO/NB algorithm uses from 51p to 82p fewer shields compared to uniform shield insertion and net ordering (US + NO), and uses from 4p to 47p fewer shields compared to separated net ordering and shield insertion (NO + SI). Furthermore, the SINO/NB solutions under practical noise bounds use from 38p to 61p fewer shields compared to SINO/NF solutions, and use up to 36p fewer shields compared to the theoretical lower bound for optimal SINO/NF solutions. Moreover, we show that the Keff model has a high fidelity versus the noise voltage computed using accurate RLC circuit models and SPICE simulations. To the best of our knowledge, it is the first work that presents an in-depth study on the automatic layout optimization of multiple nets to minimize both capacitive and inductive noise.

/pdf/simultaneous-shield-insertion-and-net-ordering-for-43mdex49m3.pdf

In this paper we present an efficient decoupling model for on-chip interconnect analysis. This model decouples multiple RLC transmission lines into independent lines with separate drivers and receivers. Based on this model we propose an efficient algorithm to solve the far end responses of multiple RLC lines. Experiments show good matching between our decoupling model and SPICE simulation. Based on the model, we further develop an Nmax algorithm to quickly determine the noise amplitudes of far end responses. Experiments show that Nmax algorithm gives conservative but reasonably accurate results compared to SPICE simulation.

/pdf/a-decoupling-method-for-analysis-of-coupled-rlc-518c6fi17e.pdf

A decoupling method for analysis of coupled RLC interconnects

Transmission line effects become increasingly significant for on-chip high-speed interconnects. Efficient and accurate transmission line models are required for analysis and synthesis of such interconnects. In this paper, we first present an efficient model for the far-end response of a single transmission line considering ramp input and capacitive loading. Our model divides the time axis into a number of regions according to the time of flight and the input rising time, and then approximates the far-end response by piecewise linear (PWL) waveform in each region. We name the resulting model as the PWL model. Experiments show that the waveform from the PWL model differs from the SPICE simulation result with the average voltage difference less than 0.9% V/sub dd/, and the PWL model is at least 1000/spl times/ faster than SPICE simulation. We further apply the PWL model to calculate the delay, rising time, and oscillation amplitude of the coplanar waveguide structure, and achieve less than 10% average error compared to SPICE simulation. Combining the PWL model and decoupling technique, we analyze the far-end response of bus structures and obtain waveform almost perfectly matching the SPICE simulation result.

/pdf/piecewise-linear-model-for-transmission-line-with-capacitive-4anwyxszyf.pdf

Piecewise linear model for transmission line with capacitive loading and ramp input

Considering a RLC interconnect model, we determine switching patterns and switching times of multiple aggressors to generate the worst case crosstalk noise (WCN) for a quiet or a noisy victim. We consider the routing direction as it has a significant impact under the RLC model. When there are no timing window constraints, we show that the commonly used superposition algorithm results in 15% underestimation on average, and propose a new SS + AS algorithm that has virtually the same complexity as the superposition algorithm but has a much improved accuracy. On average, the SS + AS algorithm only underestimates WCN by 3% compared to time-consuming simulated annealing and genetic algorithm. We also show that applying a RC model to the high-speed interconnects in the International Technology Roadmap for Semiconductors 0.10 /spl mu/m technology virtually always underestimates WCN, and the underestimation can be up to 80%. Furthermore, we extend our algorithm to consider aggressor switching and victim sampling windows. We show that the extended SS + AS algorithm well approximates WCN with 2% underestimation on average. Although the RC model usually severely underestimates WCN with timing window constraints, it does overestimate when both the aggressor switching and the victim sampling windows are small enough. We conclude that the RLC model is needed for accurate modeling of WCN in design in the multigigahertz region.

/pdf/worst-case-crosstalk-noise-for-nonswitching-victims-in-high-4pjcrasd6g.pdf

Jun Chen

Papers

Efficient In-Package Decoupling Capacitor Optimization for I/O Power Integrity

Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization

A decoupling method for analysis of coupled RLC interconnects

Piecewise linear model for transmission line with capacitive loading and ramp input

Worst case crosstalk noise for nonswitching victims in high-speed buses