A magnetoresistive element according to an embodiment includes: a first ferromagnetic layer having an axis of easy magnetization in a direction perpendicular to a film plane; a second ferromagnetic layer having an axis of easy magnetization in a direction perpendicular to a film plane; a nonmagnetic layer placed between the first ferromagnetic layer and the second ferromagnetic layer; a first interfacial magnetic layer placed between the first ferromagnetic layer and the nonmagnetic layer; and a second interfacial magnetic layer placed between the second ferromagnetic layer and the nonmagnetic layer The first interfacial magnetic layer includes a first interfacial magnetic film, a second interfacial magnetic film placed between the first interfacial magnetic film and the nonmagnetic layer and having a different composition from that of the first interfacial magnetic film, and a first nonmagnetic film placed between the first interfacial magnetic film and the second interfacial magnetic film

Magnetoresistive element and magnetic memory

Fast non-volatile memories (NVMs) will soon appear on the processor memory bus alongside DRAM. The resulting hybrid memory systems will provide software with sub-microsecond, high-bandwidth access to persistent data, but managing, accessing, and maintaining consistency for data stored in NVM raises a host of challenges. Existing file systems built for spinning or solid-state disks introduce software overheads that would obscure the performance that NVMs should provide, but proposed file systems for NVMs either incur similar overheads or fail to provide the strong consistency guarantees that applications require.

We present NOVA, a file system designed to maximize performance on hybrid memory systems while providing strong consistency guarantees. NOVA adapts conventional log-structured file system techniques to exploit the fast random access that NVMs provide. In particular, it maintains separate logs for each inode to improve concurrency, and stores file data outside the log to minimize log size and reduce garbage collection costs. NOVA's logs provide metadata, data, and mmap atomicity and focus on simplicity and reliability, keeping complex metadata structures in DRAM to accelerate lookup operations. Experimental results show that in write-intensive workloads, NOVA provides 22% to 216× throughput improvement compared to state-of-the-art file systems, and 3.1× to 13.5× improvement compared to file systems that provide equally strong data consistency guarantees.

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NOVA: a log-structured file system for hybrid volatile/non-volatile main memories

This paper will review emerging non-volatile memory (NVM) technologies, with the focus on phase change memory (PCM), spin-transfer-torque random-access-memory (STTRAM), resistive random-access-memory (RRAM), and ferroelectric field-effect-transistor (FeFET) memory. These promising NVM devices are evaluated in terms of their advantages, challenges, and applications. Their performance is compared based on reported parameters of major industrial test chips. Memory selector devices and cell structures are discussed. Changing market trends toward low power ( e.g. , mobile, IoT) and data-centric applications create opportunities for emerging NVMs. High-performance and low-cost emerging NVMs may simplify memory hierarchy, introduce non-volatility in logic gates and circuits, reduce system power, and enable novel architectures. Storage-class memory (SCM) based on high-density NVMs could fill the performance and density gap between memory and storage. Some unique characteristics of emerging NVMs can be utilized for novel applications beyond the memory space, e.g. , neuromorphic computing, hardware security, etc . In the beyond-CMOS era, emerging NVMs have the potential to fulfill more important functions and enable more efficient, intelligent, and secure computing systems.

A review of emerging non-volatile memory (NVM) technologies and applications

This tutorial introduces the basics of emerging nonvolatile memory (NVM) technologies including spin-transfer-torque magnetic random access memory (STTMRAM), phase-change random access memory (PCRAM), and resistive random access memory (RRAM). Emerging NVM cell characteristics are summarized, and device-level engineering trends are discussed. Emerging NVM array architectures are introduced, including the onetransistor?one-resistor (1T1R) array and the cross-point array with selectors. Design challenges such as scaling the write current and minimizing the sneak path current in cross-point array are analyzed. Recent progress on megabit-to gigabit-level prototype chip demonstrations is summarized. Finally, the prospective applications of emerging NVM are discussed, ranging from the last-level cache to the storage-class memory in the memory hierarchy. Topics of three-dimensional (3D) integration and radiation-hard NVM are discussed. Novel applications beyond the conventional memory applications are also surveyed, including physical unclonable function for hardware security, reconfigurable routing switch for field-programmable gate array (FPGA), logic-in-memory and nonvolatile cache/register/flip-flop for nonvolatile processor, and synaptic device for neuro-inspired computing.

Emerging Memory Technologies: Recent Trends and Prospects

In the past five decades, the semiconductor industry has gone through two distinct eras of scaling: the geometric (or classical) scaling era and the equivalent (or effective) scaling era. As transistor and memory features approach 10 nanometres, it is apparent that room for further scaling in the horizontal direction is running out. In addition, the rise of data abundant computing is exacerbating the interconnect bottleneck that exists in conventional computing architecture between the compute cores and the memory blocks. Here we argue that electronics is poised to enter a new, third era of scaling — hyper-scaling — in which resources are added when needed to meet the demands of data abundant workloads. This era will be driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration and heterogeneous integration techniques. This Perspective argues that electronics is poised to enter a new era of scaling – hyper-scaling – driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration, and heterogeneous integration techniques.

The era of hyper-scaling in electronics

According to one embodiment, a magnetic memory element includes a stacked body including first and second stacked units. The first stacked unit includes first and second ferromagnetic layers and a first nonmagnetic layer. A magnetization of the first ferromagnetic layer is fixed in a direction perpendicular to the first ferromagnetic layer. A magnetization of the second ferromagnetic layer is variable. The first nonmagnetic layer is provided between the first and second ferromagnetic layers. The second stacked unit stacked with the first stacked unit includes third and fourth ferromagnetic layers and a second nonmagnetic layer. A magnetization of the third ferromagnetic layer is variable. The fourth ferromagnetic layer is stacked with the third ferromagnetic layer. A magnetization of the fourth ferromagnetic layer is fixed in a direction perpendicular to the fourth ferromagnetic layer. The second nonmagnetic layer is provided between the third and fourth ferromagnetic layers.

Magnetic memory element and nonvolatile memory device

A method of forming a concave-convex pattern according to an embodiment includes: forming a guide pattern on a base material, the guide pattern having a convex portion; forming a formative layer on the guide pattern, the formative layer including a stacked structure formed by stacking a first layer and a second layer, the first layer including at least one element selected from a first metal element and a metalloid element, the second layer including a second metal element different from the first metal element; selectively leaving the formative layer only at side faces of the convex portions by performing etching on the formative layer; removing the guide pattern; and forming the concave-convex pattern in the base material by performing etching on the base material, with the remaining formative layer being used as a mask

Concave-convex pattern forming method and magnetic tunnel junction element forming method

Nonvolatile memory, spin-transfer torque magnetoresistive RAM (STT-MRAM) is being developed to realize nonvolatile working memory because it provides high-speed accesses, high endurance, and CMOS-logic compatibility Furthermore, programming current has been reduced drastically by developing the advanced perpendicular STT-MRAM [1] Several-megabit STT-MRAM with sub-5ns operation is demonstrated in [2] Advanced perpendicular STT-MRAM achieve ∼3× power saving by reducing leakage current in memory cells compared with SRAM for last level cache (LLC) [3] Such high-speed RAM applications, however, entail several issues: the probability of read disturbance error increases and the active power of STT-MRAM must be decreased for higher access speed Moreover, the leakage power of peripheral circuits must be decreased, because the high-speed RAM requires high-performance transistors having high leakage current in peripheral circuitry [4], limiting the energy efficiency of STT-MRAM To resolve these issues, this paper presents STT-MRAM circuit designs: a short read-pulse generator with small overhead using hierarchical bitline for eliminating read disturbance, a charge-optimization scheme to avoid excessive active charging/discharging power, and ultra-fast power gating and power-on adaptive to RAM status for reducing leakage power

7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture

A magnetic memory according to an embodiment includes: at least one memory cell comprising a magnetoresistive element as a memory element, and first and second electrodes that energize the magnetoresistive element The magnetoresistive element includes: a first magnetic layer having a variable magnetization direction perpendicular to a film plane; a tunnel barrier layer on the first magnetic layer; and a second magnetic layer on the tunnel barrier layer, and having a fixed magnetization direction perpendicular to the film plane The first magnetic layer including: a first region; and a second region outside the first region so as to surround the first region, and having a smaller perpendicular magnetic anisotropy energy than that of the first region The second magnetic layer including: a third region; and a fourth region outside the third region, and having a smaller perpendicular magnetic anisotropy energy than that of the third region

Magnetic memory and method of manufacturing the same

PROBLEM TO BE SOLVED: To provide a manufacturing method of a nonvolatile storage device that suppresses deterioration of spin injection magnetization reversing properties of a magnetoresistance effect element and has a high manufacturing yield.SOLUTION: According to one embodiment, there is provided a manufacturing method of a nonvolatile storage device that has a plurality of memory cells. Each of the plurality of memory cells has: a base layer that includes a first electrode; a magnetoresistance effect element disposed on the base layer; and a second electrode disposed on the magnetoresistance effect element. The magnetoresistance effect element includes: a first magnetic layer that is a storage layer; a tunnel barrier layer disposed on the first magnetic layer; and a second magnetic layer that is disposed on the tunnel barrier layer and is a reference layer. By irradiating a part of a surface of the second magnetic layer or a part of a surface of the first magnetic layer with an ionized gas cluster, to etch the part of the surface of the second magnetic layer or the part of the surface of the first magnetic layer.

Junichi Ito

Papers

Magnetic memory element and nonvolatile memory device

Concave-convex pattern forming method and magnetic tunnel junction element forming method

7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture

Magnetic memory and method of manufacturing the same

Manufacturing method of nonvolatile storage device