Shinobu Fujita

TL;DR: The fabrication of the first stand-alone integrated circuit combining silicon transistors and individual carbon nanotube interconnect wires on the same chip operating above 1 GHz is reported, paving the way for future multi-GHz nanoelectronics.

TL;DR: In this article, a defect-tolerance technique for TSVs-based multi-bit links through an efficient and effective use of redundancy is presented, which is ideally suited for three-dimensional network-on-chip (NoC) links.

TL;DR: In this article, the performance of high-speed on-chip graphene and MWCNT interconnects is evaluated using a low-swing signaling technique, which has been applied to improve the speed of the interconnect up to 30%.

TL;DR: In this paper, the authors present an in-depth analysis of the nanowire and nanotube device performance under process variability and show that nanowires/nanotubes are significantly less sensitive to many process parameter variations due to their inherent device structures and geometric properties.

TL;DR: STT-MRAM circuit designs are presented: a short read-pulse generator with small overhead using hierarchical bitline for eliminating read disturbance, a charge-optimization scheme to avoid excessive active charging/discharging power, and ultra-fast power gating and power-on adaptive to RAM status for reducing leakage power.