In designing synchronous circuits and memory elements, Flip-flops (FF) play an integral role. In the present era, the demand of area efficient, lesser delay, and faster devices are the major concern. This paper present the comparative study of Flip Flops in terms of area and delay. The problem of device size is very dominant today because the demand for small device size along with lesser number of transistors is increasing. And also for implementing a circuit, comparatively less number of transistors are preferred in comparison to conventionally used number of transistors, as it results in lesser number of switching activities. And smaller delay is preferred as it results in faster device along with faster response time of device. Hence, in this paper, the comparative study of various flip flops using The Clocked CMOS (C2MOS) register, True Single-Phase Clocked Register (TSPCR), Self-Gating Flip Flop, Static Flip Flop is done. The reduction in the delay is done by properly changing the size of transistor and alteration in the value of voltage. The circuits are simulated and correlated using 45nm technology.

Analytical study of high performance flip-flop circuits based on performance measurements

D-Flipflops are widely used in designing various analogue, digital and mixed signals. Different shift registers, counters and other circuits are designed using D-Flipflop. To increase the battery life time and reduce the power consumption, the voltage given to the circuit have to be decreased in the Standby mode of operation. In this paper different D Flipflops are designed using techniques like 5 transistor D-Flip Flop, Self-voltage level D-Flipflop and modified SVL (Self Voltage Level) D-Flipflop and Novel sleep transistor technique. Comparisons are made between all the designs in terms of power, delay and leakage power. All the designs are designed and simulated with the help of Cadence Virtuoso in 90nm technology. The leakage power observed in Novel Sleep Transistor technique is 93.5% less than that observed in Modified SVL Technique.

Designing a D-Flipflop Using Novel Sleep Transistor Technique

D-Flipflops are widely used in designing various analogue, digital and mixed signals. Different shift registers, counters and other circuits are designed using D-Flipflop. To increase the battery life time and reduce the power consumption, the voltage given to the circuit have to be decreased in the Standby mode of operation. In this paper different D Flipflops are designed using techniques like 5 transistor D-Flip Flop, Self-voltage level D-Flipflop and modified SVL (Self Voltage Level) D-Flipflop and Novel sleep transistor technique. Comparisons are made between all the designs in terms of power, delay and leakage power. All the designs are designed and simulated with the help of Cadence Virtuoso in 90nm technology. The leakage power observed in Novel Sleep Transistor technique is 93.5% less than that observed in Modified SVL Technique. 

This paper presents a full custom design of a 4-bit ANN processing element, implemented using 120 nm technology. The processing element consists of register, adder, and multiplier. The register is implemented using push-pull D flip-flop architecture, the adder is implemented using modified carry lookahead architecture, while the multiplier is implemented using the parallel architecture of the radix-4 booth. The processing element is fully functional and has been simulated with a 1 GHz clock frequency. The total area of the processing element is 3752.6 µm2 with the worst path delay of 305 ps.

Full Custom Layout of Neural Network Processing Element Using Push Pull D Flip Flop and Modified Carry Look Ahead Adder

Storage of digital circuit is "state" or memory. These are called sequential circuits. The most fundamental sequential circuit type that we will ponder is known as the Flip-Flop. It is ponder four distinct assortments of these gadgets and their utilization in registers and register documents, which can be considered as one type of on– CPU memory. The traditional memory, called RAM, is ordinarily not on the CPU chip. Regular Slam and its assortments, including RAM, ROM, SRAM, Measure, and SDRAM. True single-phase clock (TSPC) method of reasoning has found wide use in advanced plan. At first as a quick topology, the TSPC structure in like manner eats up less power and includes less areas than various systems. In flip-flop plan only a single transistor is being clocked by short heartbeat get ready which is known as True Single Phase Clocking (TSPC) flip-flop.

https://www.ijritcc.org/index.php/ijritcc/article/download/5308/5264

Review of Clocked Storage Elements in Digital Circuit Design

True Single Phase Clock (TSPC) is a general dynamic flip-flop that operates at high speed and consumes low power. This paper describes the design and performance analysis of 5 transistor (5T) TSPC D Flip-flop in comparision with different TSPC D Flip-flops such as; (i) MS-Negative-edge triggered TSPC D Flip-flop, (ii) Positive-edge triggered TSPC D Flip-flop with (a) 13 transistors, (b) 11 transistors, (c) 9 transistors, (d) 8 transistors, (e) 6 transistor TSPC D Flip-flops with respect to transistor density, power and delay. Finally Charge Pump with PFD is designed using 5T TSPC D Flip-flop method and functionality of the circuit is verified through simulation. A Layout of 5T TSPC D Flip-flop and Charge Pump with PFD are designed. DRC, ERC, LVS are verified with gpdk 180nm technology. All the circuits used in this paper are designed and simulated using Cadence Virtuoso Platform, with gpdk 180nm CMOS process using 1.8V supply voltage.

K. A. Sunitha

Papers

Implementation of high speed and low power 5T-TSPC D flip-flop and its application