Proceedings ArticleDOI
Implementation of high speed and low power 5T-TSPC D flip-flop and its application
H. Ashwini,S Rohith,K. A. Sunitha +2 more
- pp 0275-0279
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TLDR
In this article, the design and performance analysis of 5 transistor (5T) TSPC D Flip-flop with respect to transistor density, power, and delay are presented and simulated using Cadence Virtuoso Platform, with gpdk 180nm process using 1.8V supply voltage.Abstract:
True Single Phase Clock (TSPC) is a general dynamic flip-flop that operates at high speed and consumes low power. This paper describes the design and performance analysis of 5 transistor (5T) TSPC D Flip-flop in comparision with different TSPC D Flip-flops such as; (i) MS-Negative-edge triggered TSPC D Flip-flop, (ii) Positive-edge triggered TSPC D Flip-flop with (a) 13 transistors, (b) 11 transistors, (c) 9 transistors, (d) 8 transistors, (e) 6 transistor TSPC D Flip-flops with respect to transistor density, power and delay. Finally Charge Pump with PFD is designed using 5T TSPC D Flip-flop method and functionality of the circuit is verified through simulation. A Layout of 5T TSPC D Flip-flop and Charge Pump with PFD are designed. DRC, ERC, LVS are verified with gpdk 180nm technology. All the circuits used in this paper are designed and simulated using Cadence Virtuoso Platform, with gpdk 180nm CMOS process using 1.8V supply voltage.read more
Citations
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Proceedings ArticleDOI
Analytical study of high performance flip-flop circuits based on performance measurements
Neha Raghav,Malti Bansal +1 more
TL;DR: The comparative study of various flip flops using The Clocked CMOS (C2MOS) register, True Single-Phase Clocked Register (TSPCR), Self-Gating Flipflop, Static Flip Flop is done.
Proceedings ArticleDOI
Designing a D-Flipflop Using Novel Sleep Transistor Technique
TL;DR: In this paper , different D-Flipflops are designed using techniques like 5 transistor DFL, Self-voltage level DFL and modified SVL (Self Voltage Level) D-FLOP and Novel sleep transistor technique.
Proceedings ArticleDOI
Designing a D-Flipflop Using Novel Sleep Transistor Technique
TL;DR: In this article , different D-Flipflops are designed using techniques like 5 transistor DFL, Self-voltage level D-FLOP, modified SVL (Self Voltage Level) DFLOP and Novel sleep transistor technique.
Proceedings ArticleDOI
Full Custom Layout of Neural Network Processing Element Using Push Pull D Flip Flop and Modified Carry Look Ahead Adder
Adiwena Putra,Trio Adiono +1 more
TL;DR: In this paper, the authors present a full custom design of a 4-bit ANN processing element, implemented using 120 nm technology, which consists of register, adder, and multiplier.
Journal ArticleDOI
Review of Clocked Storage Elements in Digital Circuit Design
Ayushi Nagar,Rahul Shrivastava +1 more
TL;DR: True single-phase clock (TSPC) method of reasoning has found wide use in advanced plan and in flip-flop plan only a single transistor is being clocked by short heartbeat get ready.
References
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Journal ArticleDOI
Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler
TL;DR: A new low power and improved speed TSPC 2/3 prescaler is proposed which is silicon verified and capable of operating up to 5 GHz and ideally, a 67% reduction of power consumption is achieved when compared under the same technology at supply voltage of 1.8 V.
Journal ArticleDOI
A Low-Power Single-Phase Clock Multiband Flexible Divider
TL;DR: A low-power single-phase clock multiband flexible divider for Bluetooth, Zigbee, and IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers is proposed based on pulse-swallow topology and is implemented using a 0.18-μm CMOS technology.
Journal ArticleDOI
A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler
TL;DR: A high-speed CMOS TSPC divide-by-16/17 dual modulus prescaler with improved speed and maximum operating frequency is proposed, which is capable of operating up to 5.8 GHz.
Phase Frequency Detector and Charge Pump For DPLL Using 0.18µm CMOS Technology
Kashyap K. Patel,Nilesh D. Patel +1 more
TL;DR: In this paper, a low power phase frequency detector with a charge pump was proposed for a phase lock loop with dead zone compensation, which was realized using 0.18um CMOS technology.