An asymmetric image encryption scheme has been proposed in the fractional Fourier transform (FRT) domain, using a radial Hilbert mask in the input plane and a random phase mask based in the frequency plane. The use of a radial Hilbert mask provides an addition of extra encryption parameter along with the asymmetric scheme which is non-linear where the encryption and decryption keys are different. The encrypted image resulting from the application of FRT is attenuated by a factor and combined with the asymmetric scheme to provide an encrypted image. The decryption process is the reverse of the encryption. The designed scheme has been implemented digitally using MATLAB R2014a (8.3.0.532). By analysing the decryption results using input images the strength and efficacy of the proposed scheme has been established. The performance assessment of the method has been evaluated in terms of peak signal-to-noise ratio, mean-squared-error (MSE). The proposed scheme provides increased security.

Non-linear Cryptosystem for Image Encryption Using Radial Hilbert Mask in Fractional Fourier Transform Domain

Major operation block in any processing unit is a multiplier. There are many multiplication algorithms are proposed, by using which multiplier structure can be designed. Among various multiplication algorithms, Wallace tree multiplication algorithm is beneficial in terms of speed of operation. With the advancement of technology, demand for circuits with high speed and low area is increasing. In order to improve the speed of Wallace tree multiplier without degrading its area parameter, a new structure of Wallace tree multiplier is proposed in this paper. In the proposed structure, the final addition stage of partial products is performed by parallel prefix adders (PPAs). In this paper, five Wallace tree multiplier structures are proposed using Kogge stone adder, Sklansky adder, Brent Kung adder, Ladner Fischer adder and Han carlson adder. All the multiplier structures are designed using Verilog HDL in Xilinix 13.2 design suite. The proposed structures are simulated using ISIM simulator and synthesized using XST synthesizer. The proposed designs are analyzed with respect to traditional multiplier design in terms of area (No. of LUTs) and delay (ns).

Design and analysis of High speed wallace tree multiplier using parallel prefix adders for VLSI circuit designs

The structure of modified tree multipliers with different adders is presented. Multiplication is an important fundamental arithmetic operation in all microprocessor circuits and algorithms. Currently the speed of multipliers is limited by the speed of adders used for partial products addition. In this paper Conventional Array Multiplier and Dadda Multiplier are compared with the Wallace multiplier in terms of delay. Further a proposed sixteen bit Wallace multiplier is implemented by using Carry Select Adder (CSLA) and Binary to Excess −1 Converter (BEC) adder. The delay for Wallace multiplier using CSLA is less when compared to Wallace multiplier with BEC. These multipliers are coded in Verilog HDL, simulated and synthesized by using XILINX software 12.2 on Spartan 3E FPGA device xc3s500–5fg320.

Design of delay efficient modified 16 bit Wallace multiplier

Multipliers are major blocks in the most of the digital and high performance systems such as Microprocessors, Signal processing Circuits, FIR filters etc. In the present scenario, Fast multipliers with less power consumption are leading with their performance. Wallace tree multiplier with carry select adder (CSLA) is one of the fastest multiplier but utilizes more area. To improve the performance of this multiplier, CSLA is replaced by binary excess-1 counter(BEC) which not only reduces the area at gate level but also reduces power consumption. Area and power calculations for the Wallace tree multiplier using CSLA with BEC are giving good results compared to regular Wallace tree multiplier

Low power and area efficient Wallace tree multiplier using carry select adder with binary to excess-1 converter

This paper mainly describes the design of 8-bit Vedic multiplier and its performance comparison with existing multiplier such as i) Booth multiplier ii) Array multiplier iii) Wallace tree multiplier. Vedic calculations are the olden scheme of mathematics, which has a procedure of mathematical calculations to compute the multiplication of two 8-bit number. In this work Urdhva Tiryagbhyam (vertical and crosswise) Vedic sutra is used for multiplier design which provides better performance and consumes lesser time for computation. The Urdhva Tiryagbhyam is the finest sutra and universal one among additional sutras and which represents the different multiplication process compared to normal multiplication. In this work, Modified Carry Save Adder (MCSA) is used to compute the sum of partially generated products. It reduces the computational delay towards the addition of unfinished products. The proposed design uses the Verilog HDL to develop the algorithm. The XILINX 14.7 software tool is used to simulate and synthesize the code. The proposed design is also verified on Spartan-6 Field Programmable Gate Array (FPAGA). Finally, the proposed 8-bit multiplier design is compared with 8-bit Booth multiplier, Array multiplier and Wallace tree multiplier in terms of Area, Memory and Delay. The result shows proposed 8-bit Vedic multiplier is efficient and consumes 14.219ns time for the multiplication process which is better compared to 8-bit, Booth multiplier, Array multiplier and Wallace tree multiplier.

Design of 8 Bit Vedic Multiplier Using Urdhva Tiryagbhyam Sutra With Modified Carry Save Adder

This paper describes the design of high speed Vedic multiplier that uses the techniques of Vedic mathematics based on 16 sutras (algorithms) to improve the performance. In this paper the efficiency of Urdhva Tiryagbhyam (vertical and crosswise) Vedic method for multiplication which is different from the process of normal multiplication is presented. Urdhva-Tiryagbhyam is the most efficient algorithm that gives minimum delay for multiplication for all types of numbers irrespective of their size. Vedic multiplier is coded in Verilog HDL and stimulated and synthesized by using XILINX software 12.2 on Spartan 3E kit. Further the design of array multiplier is compared with the proposed multiplier in terms of delay, memory and power consumption.

Area efficient modified vedic multiplier

Adders play a vital role in the digital signal processing systems. The design of 32-bit adders is of high importance because 32-bit architecture is common and widely used in many digital systems and processors. In this paper, the design and the implementation of various 32-bit adders like Ripple Carry Adder (RCA), Carry Increment adder (CINA) and Carry bypass adder (CBYA) for different full adder cells is done using the Verilog HDL. The results are obtained by executing Verilog code in Xilinx 14.5 ISE for the Spartan 3E family device with speed grade −5.

Design and implementation of 32-bit adders using various full adders

This paper presents the VLSI Architecture for High-Speed 32-bit Multiplier using Vedic Mathematic sutras. Two sutras among 16 sutras of Vedic Mathematics can be applied for multiplication. Nikhilam Sutra and Urdhva-Tiryagbhyam Sutra are used to implement Vedic Multipliers. In this paper, VLSI architecture for both sutras is implemented and synthesized in Xilinx software. The delay and memory for multiplier using Urdhva-Tiryagbhyam sutra are less when compared to multiplier using Nikhilam sutra. Further, the structure of Vedic Multiplier is modified by using Binary to excess-1 code converter so as to obtain less delay for the multiplier. By replacing normal adders with Binary to excess-1 code converter in multipliers we can achieve reduction in delay.

K. Bala Sindhuri

Papers

Area efficient modified vedic multiplier

Design of delay efficient modified 16 bit Wallace multiplier

Low power and area efficient Wallace tree multiplier using carry select adder with binary to excess-1 converter

Design and implementation of 32-bit adders using various full adders

VLSI architecture for delay efficient 32-bit multiplier using vedic mathematic sutras