The Quantum-Dot Cellular Automata (QCA) is an incipient nanotechnology in contrast to the CMOS technology with appealing features like low power consumption, high speed and reduced size in implementing the architecture for the computations. QCA provides better and well-organised solution with a modern and exclusive result in performing logical computations at Nano-scale. In this paper mainly focused on design and implementation of 8 $$\times $$ 8 Vedic multiplier with the help of 4 $$\times $$ 4 Vedic multiplier using Nikhilam and Anurupayan Sutra. The simulation results achieved with the help of QCA Designer tool shows that the area and delay of the proposed 8 $$\times $$ 8 Vedic multiplier is decreased by an average of 45.8% and 72.6%, 82.5% and 80.7%, and 17.24% and 21% respectively when compared to 8 $$\times $$ 8 Array multiplier, 8 $$\times $$ 8 Wallace multiplier, and 8 $$\times $$ 8 Urdhva Tiryagbhyam Vedic multiplier. Furthermore, the proposed multiplier is implemented on Kintex-7 (KC705) FPGA board. The results revealed a reduction in area and delay compared to a well-known prior art multipliers.

An efficient design and implementation of Vedic multiplier in quantum-dot cellular automata

Multiplier is of the most important blocks of many VLSI application. So, it is required to design high performance multiplier to boost up the performance of those circuits and systems. In this work, a high performing Multiplier has been designed by using Wallace tree algorithm. The multiplier has been designed in three modules. Initially partial products are generated followed by partial products processing. Finally, final addition is computed in the 3rd module. Partial products have been generated by using AND gates. Partial products are computed by using Wallace tree logarithm. Final addition has been done by fast adder. The performance of the proposed multiplier circuit is evaluated by using 90nm CMOS technology at the Synopsys tool. The performance of the same is compared conventional multiplier circuits. The performance of the proposed adder has been found to be satisfactory.

Design and Analysis of High Performance Multiplier Circuit

Computation intensive applications such as DSP, image processing, floating point processors and communication technologies today require efficient binary multiplication which usually is the most power and time consuming block. This paper proposes an efficient design for unsigned binary multiplication to reduce delay. A 16×16-bit multiplier has been designed which is based on Vedic Karatsuba algorithm. It is optimized using adaptive and recursive approach combined with square-root-carry-select-adder. The designs have been coded in Verilog, synthesized in Cadence Genus and physically verified with Cadence Innovus in GDSII under ASIC platform.

ASIC Implementation of High-Speed Adaptive Recursive Karatsuba Multiplier with Square-Root-Carry-Select-Adder

Multipliers are basic building blocks for many arithmetic logic units, digital signal processors, coding theory units, communication systems, image processing systems etc. So multipliers designed with high speed and power efficient are essential for high performance processing units. The speed of multiplier is limited by propagation delay of adder. Therefore, design of efficient adders is critical in high performance multipliers. Vedic multipliers is one of the fastest multipliers which are focused recently. In this paper, we propose an power-delay efficient design of Vedic multiplier using adaptable Manchester Carry Chain adders (MCC) in a hierarchal approach. The proposed Vedic multiplier design using MCC is evaluated and analyzed in terms of power, delay and area in a standard 45nm CMOS technology in CADENCE. The proposed Vedic multiplier design using MCC has lower power-delay product requirement than existing Vedic multiplier architectures.

Power-delay-area efficient design of vedic multiplier using adaptable manchester carry chain adder

The design of a high-speed Wallace tree multiplier has been always challenging on a system design level. In this paper, we proposed a high-speed Wallace tree multiplier using 7:3 and 5:3 counter. Instead of the traditional architecture of the Wallace tree multiplier, we focused on the arrangement of partial product matrix and optimization technique in the reduction tree matrix. The proposed work starts with generation of a partial product matrix and continues until achieves two rows of the partial product matrix. The last two rows of Wallace tree multiplier is added with the help of parallel prefix Ladner-Fischer adder. Results show efficiency of Wallace tree multiplier in terms of hardware and speed. The synthesis and verification of the design is done using Xilinx ISE 14.7. For implementation, Spartan 3E FPGA device xc3s500e-5fg320 is used.

Verilog Implementation of High-Speed Wallace Tree Multiplier

The structure of modified tree multipliers with different adders is presented. Multiplication is an important fundamental arithmetic operation in all microprocessor circuits and algorithms. Currently the speed of multipliers is limited by the speed of adders used for partial products addition. In this paper Conventional Array Multiplier and Dadda Multiplier are compared with the Wallace multiplier in terms of delay. Further a proposed sixteen bit Wallace multiplier is implemented by using Carry Select Adder (CSLA) and Binary to Excess −1 Converter (BEC) adder. The delay for Wallace multiplier using CSLA is less when compared to Wallace multiplier with BEC. These multipliers are coded in Verilog HDL, simulated and synthesized by using XILINX software 12.2 on Spartan 3E FPGA device xc3s500–5fg320.

Design of delay efficient modified 16 bit Wallace multiplier

This paper presents the VLSI Architecture for High-Speed 32-bit Multiplier using Vedic Mathematic sutras. Two sutras among 16 sutras of Vedic Mathematics can be applied for multiplication. Nikhilam Sutra and Urdhva-Tiryagbhyam Sutra are used to implement Vedic Multipliers. In this paper, VLSI architecture for both sutras is implemented and synthesized in Xilinx software. The delay and memory for multiplier using Urdhva-Tiryagbhyam sutra are less when compared to multiplier using Nikhilam sutra. Further, the structure of Vedic Multiplier is modified by using Binary to excess-1 code converter so as to obtain less delay for the multiplier. By replacing normal adders with Binary to excess-1 code converter in multipliers we can achieve reduction in delay.

R. Balasaikesava

Papers

Design of delay efficient modified 16 bit Wallace multiplier

VLSI architecture for delay efficient 32-bit multiplier using vedic mathematic sutras