A 2-D subband decoder has been designed for real-time video decompression in low-power applications. The chip is capable of reconstructing four levels of hierarchical subband structures for images up to 256 pixels wide. The chip's maximum performance decodes 60 M pixels per second of color RGB video output with a 5 V supply and 120 MHz clock frequency. For portable applications with a resolution of 176 pixels wide, 240 lines, and 30 frames/s color video, the chip dissipates less than 1.2 mW with a 1 V supply. Besides the reduced supply voltage, the low power consumption is achieved through algorithmic innovations for energy conservation. Higher-resolution images can be decoded by cascading multiple chips in parallel each operating on a 256 pixel wide image slice.

A 1.2 mW video-rate 2-D color subband decoder

Systems containing both analog and digital functions have been investigated with the purpose of realizing mixed-signal integrated circuits with higher levels of functionality and integration. In most cases, such mixed-signal systems are inherently multirate because of the different sampling rates employed at various stages of the system. The multirate concepts have been used for traditional applications, such as subband coding and narrowband filter design. Some unconventional applications of multirate signal processing are also emerging, both for converting between analog samples and digital words, and for realizing processing functions in an easier and more economical way than would be possible using purely digital or analog techniques. This paper reviews fundamental multirate concepts, discusses some developments in this area of integrated multirate analog-digital systems, and outlines some possible future directions for research and application.

Multirate analog-digital systems for signal processing and conversion

A folded very large scale integration (VLSI) architecture is presented for the implementation of the two-dimensional discrete wavelet transform, without constraints on the choice of the wavelet-filter bank. The proposed architecture is dedicated to flexible block-oriented image processing, such as adaptive vector quantization used in wavelet image coding. We show that reading the image along a two-dimensional (2-D) pseudo-fractal scan creates a very modular and regular data flow and, therefore, considerably reduces the folding complexity and memory requirements for VLSI implementation. This leads to significant area savings for on-chip storage (up to a factor of two) and reduces the power consumption. Furthermore, data scheduling and memory management remain very simple. The end result is an efficient VLSI implementation with a reduced area cost compared to the conventional approaches, reading the input data line by line.

An efficient VLSI architecture for 2-D wavelet image coding with novel image scan

Our present ability to work with video has been confined to a wired environment, requiring both the video encoder and decoder to be physically connected to a power supply and a wired communication link. This paper presents a portable video-on-demand system capable of delivering high-quality image and video data in a wireless environment. The discussion will focus on both the architectural and circuit design techniques developed for implementing a high-performance, error-resistant video compression/decompression system at power levels that are two orders of magnitude below existing solutions. This low-power video compression system not only provides a compression efficiency better than industry standards, but also embeds a high degree of error tolerance in the compression algorithm itself to guard against transmission errors often encountered in wireless communication.

A wireless portable video-on-demand system

This paper describes the design process of a chip set which performs real-time video decompression for wireless portable applications and concentrates on four critical aspects of the design: compression algorithm development, control complexity, programmability, and throughput. For each of these design areas, this paper evaluates the design trade-offs between low power, compression efficiency, and throughput, which are the three main requirements for wireless portable video. The chip set consists of a subband reconstruction chip and a pyramid vector quantization (PVQ) decoder chip and requires no external memory support or frame buffer. For portable applications with a resolution of 176 pixels wide, 240 lines, and 30 frames per second color video, the chip set, operating at a 1.35 V supply, dissipates less than 9 mW.

Design of a low power video decompression chip set for portable applications

A chip set for 2D subband filtering of HDTV signals has been designed, fabricated and successfully tested. The two chips perform 10*14 quadrature mirror filtering for analysis filtering at the coder and synthesis filtering at the decoder. In order to achieve a very compact realization, the architectures utilize all a priori known properties of the filter algorithm. A 2D polyphase filter structure reduces the processing clock rate from the 72-MHz sampling rate to a moderate 18 MHz. The memory for vertical filtering is realized by on-chip parallel shift registers with multiphase clocking. A small silicon area for the filter arithmetic is achieved by application of carry save adder trees with fixed filter coefficients represented by canonical signed digits. A complete filterbank for luminance and chrominance signals consists of four identical chips, each with 450 000 transistors on 92 mm/sup 2/. >

VLSI chip set for 2D HDTV subband filtering with on-chip line memories

Key components for implementation of HDTV subband coding schemes are filter banks for band splitting at the transmitter side and for band synthesis at the receiver side. The authors deal with VLSI architectures and implementations of these filters. To reduce hardware cost and size, VLSI realizations of filter banks by dedicated circuits are considered. The impact of the filter algorithms, architectural structures and circuit technique on the implementation is explained. In particular, the advantages of quadrature mirror filters (QMFs) for the hardware implementation of two-dimensional HDTV filter banks are presented. The potential of dedicated circuit design with consideration of all a priori knowledge is illustrated for a 14*10 tap QMF filterbank with on-chip line memories. >

VLSI architectures of two-dimensional filters for HDTV coding

VLSI architectures of filterbanks necessary for an HDTV subband codec have been investigated. Different techniques have been combined in order to achieve a compact realization. The application of special QMF structures results in a further reduction of hardware expense. High clocking rates are handled using two dimensional polyphase filterbanks in combination with pipelining and parallel processing. An architecture suitable for one-chip implementation of a 10 x 14 tap QM filterbank has been developed.

VLSI architectures of filterbanks for subband coding of hdtv signals

VLSI architectures of jilterbanks necessary for an HDTV subband codec have been investigated. Different techniques have been combined in order to achieve a compact realization. The application of special QMF structures results in a further reduction of hardware ex- pense. High clocking rates are handled using two dimen- sional polyphase filterbanks in combination with pipeli- ning and parallel processing. An architecture suitable for one-chip implementation of a 10 x 14 tap QM filter- bank has been developed.

subband coding of of filterbanks HDTV signals

Subband coding is frequently proposed for source coding of HDTV. Key components for the compact realization of subband codecs are VLSI filterbanks for analysis and synthesis filtering. Avoiding programmability the development and application of dedicated subband filterbanks can significantly reduce hardware expense. For 2D Quadrature Mirror Filterbanks with 14×10 taps, a chip set with on-chip line memories and synchronous FIFOs has been developed using a 1.2?m-CMOS technology. Only two identical ICs each with about 450,000 transistors and a chip area of 92mm2 are necessary for one filterbank. The implementation is adapted to the systems parameters of interlaced scanning but the architecture can easily be extended to the processing of future progressive HDTV.

K. Grüger

Papers

VLSI chip set for 2D HDTV subband filtering with on-chip line memories

VLSI architectures of two-dimensional filters for HDTV coding

VLSI architectures of filterbanks for subband coding of hdtv signals

subband coding of of filterbanks HDTV signals

VLSI Realization of 2D HDTV Subband Filterbanks with on-Chip Line Memories and FIFOs