In a CMOS image sensor featuring a lateral overflow integration capacitor in a pixel, which integrates the overflowed charges from a fully depleted photodiode during the same exposure, the sensitivity in nonsaturated signal and the linearity in saturated overflow signal have been improved by introducing a new pixel circuit and its operation. The floating diffusion capacitance of the CMOS image sensor is as small as that of a four transistors type CMOS image sensor because the lateral overflow integration capacitor is located next to the reset switch. A 1/3-inch VGA format (640/sup H//spl times/480/sup V/ pixels), 7.5/spl times/7.5 /spl mu/m/sup 2/ pixel color CMOS image sensor fabricated through 0.35-/spl mu/m two-poly three-metal CMOS process results in a 100 dB dynamic range characteristic, with improved sensitivity and linearity.

A sensitivity and linearity improvement of a 100-dB dynamic range CMOS image sensor using a lateral overflow integration capacitor

A CMOS image sensor that can operate in both linear and logarithmic mode is described. Two sets of data are acquired and combined in the readout path to render a high dynamic range image. This is accomplished in real-time without the use of frame memory. A dynamic range in excess of 120 dB was achieved at 26 frames/s (352times288-array). The system addresses the problems of high fixed pattern noise (FPN), slow response time, and low signal-to-noise ratio (SNR) in logarithmic mode. FPN has been effectively reduced by single and two parameter calibration, the latter achieving FPN of 2% per decade. A novel on-chip method of deriving a reference point has been implemented. The system is fabricated in a 0.18-mum 1P4M process and achieves a pixel pitch of 5.6 mum with 7 transistors per pixel

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Extended Dynamic Range From a Combined Linear-Logarithmic CMOS Image Sensor

A 2.6times2.6mm2 image sensor fabricated in 0.35mum 2P3M CMOS contains 64times64 pixels with 20times20mum2 pixel size and has an extended dynamic range of over 200dB. This DR is equivalent to the incident light ranging from about 10-2 to 108 lx with the lens iris fixed

A 200dB Dynamic Range Iris-less CMOS Image Sensor with Lateral Overflow Integration Capacitor using Hybrid Voltage and Current Readout Operation

In this work, we have developed an image sensor capable of shooting both dark- and bright-objects in one synthesized frame without necessitating any buffer memories Multiply acquired signals with different exposure periods can be synthesized in each pixel, in which a feedback loop circuit is incorporated The pixel feedback loop comprises a storage capacitor, a feedback capacitor and pass transistors This configuration enables repetition of the image acquisition process, ie exposure, signal storage during the next exposure and synthesis of the successively exposed signals, as many times as needed

A 140dB-Dynamic-Range MOS Image Sensor with In-Pixel Multiple-Exposure Synthesis

During the collection operation for the imaging data of the optical image supplied to the light receiving unit in which the vertical light receiving sections are horizontally arranged, each vertical light receiving section having the light receiving devices arranged vertically therein, among the integration circuit, the buffer circuit, and horizontal reading-out section, which are arranged in each horizontal signal processing section, the integration circuit and the buffer circuit are rendered at non-operation state during the horizontal reading-out operation controlled by the timing control section, so that power is not consumed substantially during the horizontal reading-out operation. As a result, the image picking-up of the optical image supplied to the light receiving unit can be executed with a high S/N ratio and low power consumption, thereby providing a solid-state imaging apparatus which is capable of picking-up the image with a high S/N ratio and achieving a reduction in power consumption.

Solid-state imaging apparatus

A combined linear and logarithmic image sensor is implemented in a 0.35 /spl mu/m 1P3M technology. The pixel is 7.5/spl times/7.5 /spl mu/m/sup 2/ with a 37% fill factor and contains only 4 transistors. Offset calibration in the logarithmic region is realized by using electrical charge injection into the photodiode. The sensor achieves 120 dB DR and the offset calibration reduces the FPN from 13 mV to 5 mV.

K. Hara

Papers

A linear-logarithmic CMOS sensor with offset calibration using an injected charge signal