

The advent of High Performance Computing (HPC) applications and big data
applications has made it imparitive to develop hardware that can match the computing demands. In
such high performance systems, the high speed multipliers are the most sought after components. A
compressor is an important part of the multiplier; it plays a vital role in the performance of multiplier,
also it contributes to the efficiency enhancement of an arithmetic circuit. The 5:2 compressor circuit
design proposed here improves overall performance and efficiency of the arithmetic circuits in
terms of power consumption, delay and power delay product. The proposed 5:2 compressor circuit
was implemented using both CMOS and Carbon Nano Tube Field Effect Transistor (CNTFET) technologies
and it was observed that the proposed circuit has yielded better results with CNTFETs as
compared to MOSFETs.



The proposed 5:2 compressor circuit was designed with CMOS technology
simulated at 45 nm with voltage supply 1.0 V and compared it with the existing 5:2 compressor
designes to validate the improvements. Thereafter, the proposed design was implemented with CNTFET
technology at 32 nm and simulated with voltage supply 0.6 V. The comparision results of proposed
5:2 compressor with existing designs implemented using CMOS. The results also compare the
proposed design on CMOS and CNTFET technologies for parameters like power, delay, power delay
product.



It can be concluded that the proposed 5:2 compressor gives better results as compared
to the existing 5:2 compressor designs implemeted using CMOS. The improvement in power, delay
and power delay product is approx 30%, 15% and 40% respectively. The proposed circuit of 5:2
compressor is also implemented using CNTFET technology and compared, which further enhances
the results by 30% (power consumption and PDP). Hence, the proposed circuit implemented using
CNTFET gives substantial improvements over the existing circuits.


High-Performance Low-Power 5:2 Compressor With 30 CNTFETs Using 32 nm Technology

Low power has arisen as a chief topic in these days and hardware enterprises. Power dissipation has become a significant thought as execution and zone of VLSI Chip plan. In this paper, a design of low power for footed quasi resistance scheme in 45nanometer VLSI technology, using appropriate standard digital gates with 45nm technology, considering footed quasi resistance technique for nanoscales is introduced. Transition of logic 1 and 0 is the main problem in the cascading circuits, this problem can solved by employing a basic inverter called as Domino logic at output.Due to the precharge propagation the power dissipation is observed in domino logic, this will be resolved using PDB (Pseudo Dynamic Buffer) model. With the help of PDB nearly 67% of power saved. Even though PDB is succeeded in precharge propagation, it fails in logic transition, this may results erroneous output during cascading. With contracting technology, power utilization can decreased and over all power of the executives on chip are the critical difficulties below 100nm because of expanded intricacy. In this paper execution of low power circuit scheme for footed quasi resistance plot in 45nm VLSI technology. In this paper we will actualize and recreate low power circuit scheme for footed quasi resistance plot in 45nm VLSI technology.

/pdf/low-power-circuit-design-for-footed-quasi-resistance-scheme-6bmx6it1u6.pdf

Low Power Circuit Design for Footed Quasi Resistance Scheme In 45NM VLSI Technology

In this paper, approximate adders were proposed for DSP processors. DSP processors are mainly composed of adders and multipliers at bottom level. The power is minimized in transistor level design. Proposed adders have less power dissipation when compared to existing approximate adders. Results have shown that the proposed adders have less PDP with more accuracy. The circuits were simulated in Cadence virtuoso tool under 45 nm CMOS technology. Supply voltage is + 0.5 V.

Energy-efficient approximate adders for DSP applications

In VLSI design vacillating the parameters results in variation of critical factors like area, power and delay. The dominant sources of power dissipation in digital systems are the digital multipliers. A digital multiplier plays a major role in a mixture of arithmetic operations in digital signal processing applications hinge on add and shift algorithms. In order to accomplish high execution speed, parallel array multipliers are comprehensively put into application. The crucial drawback of these multipliers is that it exhausts more power than any other multiplier architectures. Montgomery Multiplication is the popularly used algorithm as it is the most efficient technique to perform arithmetic based calculations. A high-speed multiplier is greatly coveted for its extraordinary leverage. The primary blocks of a multiplier are basically comprised of adders. Thus, in order to attain a significant reduction in power consumption at the chip level the power utilization in adders can be decreased. To obtain desired results in performance parameters of the multiplier an efficient and dynamic adder is proposed and incorporated in the Montgomery multiplier. The Carbon Nanotube field effect transistor (CNTFET) is a promising new device that may supersede some of the fundamental limitations of a silicon based MOSFET. The architecture has been designed in 130nm and 32nm CMOS and CNTFET technology in Synopsys HSpice. The analysed parameters that are considered in determining the performance are power delay product, power and delay and comparison is made with both the technologies.The simulation results of this paper affirmed the CNTFET based Montgomery multiplier improved power consumption by 76.47% ,speed by 72.67% and overall energy by 67.76% as compared to MOSFET-based Montgomery multiplier.

/pdf/performance-analysis-of-montgomery-multiplier-using-32nm-19mqoowvcj.pdf

Performance Analysis of Montgomery Multiplier using 32nm CNTFET Technology

This paper presents design of 14-T 1-bit full adder power
efficient Pass Transistor Logic (PTL) based stable circuit. Due to compact
architecture, power consumption is low and response is faster. MC (Monte
Carlo) shows that the circuit is more reliable against any statistical variations

Design of power efficient stable 1-bit full adder circuit

One of the most crucial components in the computing devices is the full adders. The efficiency and effectiveness of arrays of full adders is essential; thus making it sensible to put in a reasonable effort towards improvisation of computational devices. In this paper, a new 1-BIT Full Adder (FA) with a combination of pass transistor logic and transmission gate logic is suggested. This new hybrid adder is having only 18 transistors. The proposed full adder is a CNTFET based design and also implemented 8-BIT Ripple carry Adder (RCA) at 32 nm CNTFET model files using the Cadence virtuoso tool.

K. S. Jitendra

Papers

A new low-power full-adder cell for low voltage using CNTFETs