A TANK filter is provided for a lead wire of an active medical device (AMD). The TANK filter includes a capacitor in parallel with an inductor. The parallel capacitor and inductor are placed in series with the lead wire of the AMD, wherein values of capacitance and inductance are selected such that the TANK filter is resonant at a selected frequency. The Q of the inductor may be relatively maximized and the Q of the capacitor may be relatively minimized to reduce the overall Q of the TANK filter to attenuate current flow through the lead wire along a range of selected frequencies. In a preferred form, the TANK filter is integrated into a TIP and/or RING electrode for an active implantable medical device.

Tank filters placed in series with the lead wires or circuits of active medical devices to enhance mri compatibility

An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.

Methods and apparatus for packaging integrated circuit devices

An integrally packaged optronic integrated circuit device ( 310 ) including an integrated circuit die ( 322 ) containing at least one of a radiation emitter and radiation receiver and having top and bottom surfaces formed of electrically insulative and mechanically protective material, at least one of the surfaces ( 317 ) being transparent to radiation, and electrically insulative edge surfaces ( 314 ) having pads.

Integrated circuit device

Several wafer level chip scale package (WLCSP) technologies have been developed which generate fully packaged and tested chips on the wafer prior to dicing. Many of these technologies are based on simple peripheral pad redistribution technology followed by attachment of 0.3-0.5 mm solder balls. The larger standoff generated by these solder balls result in better reliability for the WLCSP's when underfill is not used than for equivalent flip chip parts. Rambus RDRAM and integrated passives are two applications that should see wide acceptance of WLCSP packages.

Wafer level chip scale packaging (WL-CSP) : An overview

A packaged integrated circuit (10) and method for producing thereof including an integrated circuit substrate lying in a substrate plane (24) and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface (20) and at least some of the plurality of electrical contacts extending onto the second planar surface (22).

Packaged integrated circuits and methods of producing thereof

The increasing demands on future electronic products require more efficient system integration technologies. Especially the package density gap at board level with the high integrated circuits (ICs) on the one hand and the discrete passive components on the other has to be closed by new packaging technologies which integrate the passive components into the substrate, an interposer or the IC itself. This paper presents investigations for the common integration of inductors, resistors, capacitors as well as passive filter structures in a thin film build up, based on copper and benzocyclobutene (BCB). Technologies from wafer level packaging were adapted for manufacturing of the integrated components. The examinations were carried out with special focus on integrated coils and passive filter structures. Build up, design, processing as well as results of the electrical characterization of the integrated components are described in detail. Furthermore, an integrated passive device (IPD) for application as a filter element in the Bluetooth band is presented.

https://www.researchgate.net/profile/Herbert_Reichl/publication/4084249_Thin_film_integration_of_passives_-_single_components_filters_integrated_passive_devices/links/0deec5314740213bfc000000.pdf

Thin film integration of passives - single components, filters, integrated passive devices

Size reduction is one of the main driving forces for packaging in nearly all electronic applications. The interaction of size reduction with highest functionality and high reliability is also predominant for all microelectronic systems. Therefore a synergism of optimal product design, smallest single chip package and board technology will give the best solution. Wafer level CSP will be the best solution for single chip packaging matching all requirements for electronic systems and reducing total cost.

Wafer-level chip size package (WL-CSP)

Integrated passives have become increasingly popular in the last years. Especially wafer level packaging technologies offer an interesting variety of different possibilities for the implementation of integrated passive components. In this context particularly the fabrication of integrated passive devices (IPDs) represents a promising solution regarding the reduction of size and assembly costs of electronic systems in package (SiP). These IPDs combine different passive components (R, L, C) in one subcomponent to be assembled in one step by standard technologies like SMD or flip chip. In this paper the wafer level thin film fabrication of such IPDs (WL-IPDs) will be discussed. After a brief overview of the different possibilities for the realization of IPDs using wafer level packaging technologies two fabricated WL-IPDs will be presented. Design, technological realization as well as results from the electrical characterization will be discussed.

http://ieeexplore.ieee.org/iel5/9844/31024/01442003.pdf

Fabrication of application specific integrated passive devices using wafer level packaging technologies

A planar integration technology of ultra-thin bare dice in a Wafer-Level Thin-Film technology to yield a high-dense module is presented here. This Thin Chip Integration (TCI) technology consists of one or more ultra-thin chips which are stacked on a larger sized standard thick chip and which are interconnected by a thin film routing. The dice are glued on a carrier chip on wafer-level. A standard thin film multilayer which was developed for a redistribution process is realized in a planar fashion on top of the embedded system. The metallization is based on a Ti:W / Cu tie layer, which is subsequently electroplated. Cyclotene 4000 (the Photo-BCB from The Dow Chemical Company) is used as interlevel low k dielectric. This unique module concept can lead to new applications that would be not feasible before. It will lead the packaging world to new 3-D packages.

K. Scherpinski

Papers

Thin film integration of passives - single components, filters, integrated passive devices

Wafer-level chip size package (WL-CSP)

Wafer-level chip size package (WL-CSP)

Fabrication of application specific integrated passive devices using wafer level packaging technologies

Thin Chip Integration (TCI-modules) : A novel technique for manufacturing three dimensional IC-packages