Kai Zoschke

TL;DR: In this paper, analytical, numerical-, and measurement-based methods for extracting the resistance, inductance, capacitance, and conductance of through silicon vias (TSVs) are classified, quantified, and compared from 100 MHz to 100 GHz.

TL;DR: In this article, the fabrication steps for wafer level processing of silicon interposers with copper filled TSVs as well as their wafer-level assembly with IC components are presented, and special focus is drawn on the TSV formation process including via etching, isolation and filling, front side high density wiring and subsequent backside processing of the thin TSV wafers.

TL;DR: In this article, the fabrication of integrated passive devices (IPDs) using wafer level thin film fabrication is discussed, and a brief overview of the different possibilities for the realization of IPDs using Wafer level packaging technologies is presented.

TL;DR: The power receiving coils presented in this paper were designed to maximize the inductance and quality factor of the coils and microfabricated using polymer based thin film technologies.

TL;DR: In this article, the polyimide material HD3007 is used for temporary bonding of silicon wafers to carrier wafer by using a thermo compression process and two de-bonding concepts based on laser assisted and solvent assisted release processes are presented.