Microvia filling by copper electroplating using diazine black as a leveler

Filling mechanism in microvia metallization by copper electroplating

Microvia filling by copper electroplating was carried out using a plating bath containing a suppressor and a leveler without an accelerator. The required accelerator was adsorbed onto the copper seed layer of the microvia in a predipping bath before the filling plating. This pretreatment is similar to the self-assembled monolayer of thiol molecules that forms on a copper surface. The suppressor was poly(ethylene glycol) (PEG), and five levelers, namely, Janus green B, diazine black, methylene violet, safranine O, and Alcian blue, were employed to screen for the best plating formula suitable for a plating process in which no accelerator was present in the plating solution. The thiol molecule employed in this work was 3-mercapto-1-propanesulfonate (MPS). The electrochemical behaviors of various plating formulas were characterized using a galvanostatic measurement on a copper electrode at different rotating speeds. Results indicated that the MPS adlayer is transferable onto the surface of the copper deposit and can be displaced by the PEG-C1-leveler. The displacement rate depends on the molecular structure of the added leveler. This plating process has the potential to greatly reduce the plating time of microvia filling.

https://iopscience.iop.org/article/10.1149/1.3147273/pdf

Copper Fill of Microvia Using a Thiol-Modified Cu Seed Layer and Various Levelers

Through holes (THs) with different shapes were formed by laser drilling on a printed circuit board to evaluate the filling capability of two copper plating formulas. The shapes of these THs were cylindrical, V- and X-shaped. Two copper plating formulas, accelerator-free formula (AFF) and accelerator-containing formula (ACF), were employed in this work. The AFF contained only one organic additive and the ACF was composed of multiorganic additives. The electrochemical characteristics of the AFF were investigated by cyclic voltammetry, which could be utilized to explain the results of filling plating. The plating results showed that the cylindrical TH could be fully filled using AFF. However, the V- and X-shaped THs could be fully filled using ACF. TH and microvias could be simultaneously filled in one plating bath using the AFF. A filling mechanism based on an adsorption/ consumption/diffusion mode was proposed to explain these plating results.

Through-Hole Filling by Copper Electroplating

Preface (Kazuo Kondo) PART 1 Copper electrodepositon and additive chemistry Chapter 1 - Copper electrodeposition (Masayuki Yokoi) Chapter 2 - Suppression effect and Additive Chemistry (Masayuki Yokoi) Chapter 3- Acceleration effect (Dale P. Barkey) Chapter 4- Modeling and Simulation ( Yutaka Kaneko) PART 2 Copper on chip metallization Chapter 5- Frontiers of Cu Electrodeposition and Electroless Plating for On-Chip Interconnects (James R. Rohan) Chapter 6- Microstructure of Evolution of Copper in Nano-scale Interconnect Features (James Kelly, Christopher Parks, James Demarest, and Christopher Penny) Chapter 7- Direct Copper Plating (Aleksandar Radisic and Philippe M. Vereecken) Part 3 - Through Silicon Via and Other Methods Chapter 8- Through Silicon Via (Kazuo Kondo) Chapter 9- Build-up Printed Wiring board (Kiyoshi Takagi a and Toshkazu Okubo) Chapter 10- Copper Foil Smooth on Both Sides for Lithium Ion Battery (Akitoshi Suzuki and Jun Shinozaki) Chapter 11- Through hole plating (Wei-Ping Dow)

Copper electrodeposition for nanofabrication of electronics devices

Printed Wiring Boards (PWB) made by Sequential Build-Up (SBU) processes have found a wide application in semiconductor packaging substrates and system in package substrates, besides usage as a conventional printed wiring board. Its capability for high density circuits can contain multi-functional electronic circuits within a small surface area and can achieve light weight and low-profile products with improved electric characteristics. A number of processes and materials were developed and are used for each application in each electronic product. The advancement of printed wiring boards is expected to continue, driven by the requirements from electronic products. Technical development activities are needed to satisfy these requirements. Activities are still high in the development of embedded passive technology, which will equip printed wiring boards with the functions of passive components resistance (R), capacitance (C) and inductance (L) - as well as the conventional interconnection functions of conductors between components. This technology will dramatically change the structure of printed wiring boards and complicate the fabrication processes. Material development will be a key issue in the case of embedded resistors and capacitors.

K. Takagi

Papers

Development of sequential build-up multilayer printed wiring boards in Japan