A modular Vedic multiplier architecture for model-based design and deployment on FPGA platforms

Low power single precision BCD floating–point Vedic multiplier

Experimental setup of stretchable arid dry pad sensors for the signal acquisition fir filter design using Vedic approach

High speed Power efficient Vedic arithmetic modules on Zedboard-Zynq-7000 FPGA

Internet of things applications demand reusable modular designs with low-power consumption. Furthermore, many emerging applications, such as image recognition using machine learning, are low-accuracy tolerant. For these applications, the IEEE-754 half-precision arithmetic is becoming a relevant option for low-power, low-computational cost designs. This article presents a half-precision floating-point multiplier. It is implemented on 130 nm CMOS ASIC technology. The proposed multiplier IP core exhibits low-power consumption, small silicon area, and its accuracy is IEEE-754 compliant.

Half-Precision Floating-Point Multiplier IP Core Based on 130 Nm CMOS ASIC Technology

Floating-point arithmetic plays major role in computer systems. Many of the digital signal processing applications use floating-point algorithms for execution of the floating-point computations and every operating system is answerable practically for floating-point special cases like underflow and overflow. The single precision floating point arithmetic operations are multiplication, division, addition and subtraction among all these multiplication is extensively used and involves composite arithmetic functions. The single precision (32-bit) floating point number split into three parts, Sign part, and Exponent part and Mantissa part. The most significant bit of the number is a sign bit and it is a 1-bit length. Next 8-bits represent the exponent part of the number and next 23-bits represent the mantissa part of the number. Mantissa part needs large 24-bit multiplication. The performance of the single-precision floating point number mostly based on the occupied area and delay of the multiplier. In this paper, a novel approach for single-precision floating multiplier is developed by using Urdhva Tiryagbhyam technique and different adders to decrease the complexity of mantissa multiplication. This requires less hardware for multiplication compared to that conventional multipliers and used different regular adders like carry select, carry skip adders and parallel prefix adders for exponent addition. Further, the performance parameters comparison was done in terms of area and delay. All modules are coded by using Verilog HDL and simulated with Xilinx ISE tool.

Comparative study on performance of single precision floating point multiplier using vedic multiplier and different types of adders

Floating-point arithmetic plays major role in computer systems. The single precision floating point arithmetic operations are multiplication, division, addition and subtraction. Among all these multiplication is extensively used and involves composite arithmetic functions. The single precision (32-bit) floating point number split into three parts namely Sign part, and Exponent part and Mantissa part. The most significant bit of the number is a sign bit and it is a 1-bit length. Next 8-bits represent the exponent part of the number and next 23-bits represent the mantissa part of the number. Mantissa part needs large 24-bit multiplication. The performance of the single-precision floating point number mostly based on the occupied area and delay of the multiplier. In this paper, performance comparison of multiplexer based single precision floating point multiplication using Array, Wallace tree and Vedic multipliers is done in terms of area and delay. These floating point multipliers modules are programmed and synthesized using Verilog in Xilinx ISE Simulator. Maximum propagated path delay and number of slices required on FPGA are compared for different multipliers. From the result it is concluded that Multiplexer based Vedic multiplier method has a great impact on improving the speed and reducing the area required on FPGA.

Comparative performance analysis of multiplexer based single precision floating point multipliers

Compressor models are used to perform arithmetic operations like multiplication, addition etc. in digital signal processing applications such as Fast Fourier Transform, Convolution and Filtering. In order to achieve the high speed, the optimization takes place in all abstraction levels. In this paper, single precision floating point multiplication is developed using different compressor architectures to achieve high speed. Further, first, floating point multipliers are developed with normal 4:2 conventional compressors using XOR gates and further the same multipliers are developed using modified Compressors with XOR-XNOR gates and Multiplexers to achieve optimized delay and area. All the models are coded with Verilog HDL and implemented using Xilinx ISE.

Comparative analysis of single precision floating point multiplication using compressor techniques

High speed multipliers are essential in all computational units such as Arithmetic Logic Unit(ALU), Multiply Accumulate Unit and Digital Signal Processing (DSP) applications. In general, the performance of any DSP system is limited by its multiplication performance. Hence, the speed and power efficient multiplier algorithms are highly demanded in present scenario. In this Paper, high speed multipliers are designed by using binary counters based on symmetric stacking. In this work, 16-bit Wallace tree multiplier is considered for the analysis using conventional counters and symmetric stacking-based counters. Further, the performance is compared in terms of delay, area. All the blocks used in this work are programmed using Verilog HDL and they are Synthesized using Xilinx.

High Speed Multipliers using Counters based on Symmetric Stacking

Floating point operations like multiplication, division, addition and subtraction are important in digital signal processing applications. Out of all these, frequently used operation is multiplication and it changes the performance of single precision floating point multiplication in terms of delay and area. In this paper, performance analysis of single precision floating point multiplier is done by using Karatsuba algorithm with Vedic technique for multiplication and different Parallel Prefix adders like Sklansky, Brent-Kung and Knowles adders for exponent addition. This combination provides lesser area to compute multiplication compared to that existing multipliers. Further, the performance parameters comparison is done in terms of area and delay. The entire modules of single precision floating point multiplier are developed with Verilog HDL and synthesized with Xilinx ISE tool.

K V Gowreesrinivas

Papers

Comparative study on performance of single precision floating point multiplier using vedic multiplier and different types of adders

Comparative performance analysis of multiplexer based single precision floating point multipliers

Comparative analysis of single precision floating point multiplication using compressor techniques

High Speed Multipliers using Counters based on Symmetric Stacking

Design and analysis of single precision floating point multiplication using Karatsuba algorithm and parallel prefix adders