This paper presents a tutorial overview of ΣΔ modulators, their operating principles and architectures, circuit errors and models, design methods, and practical issues. A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge ΣΔ architectures, with emphasis on their application to the next generation of wireless telecom systems.

Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

A sixth-order dc-to-1 GHz tunable continuous-time lowpass/bandpass ΔΣ ADC in 65-nm CMOS targeting RF and IF digitizing applications is presented. The ADC achieves 150-MHz bandwidth at 450-MHz center frequency with 74-dB dynamic range at 4-GHz sampling frequency while consuming 550 mW. This performance is enabled by a reconfigurable LC and active-RC modulator structure, fifth-order and seventh-order feedforward operational amplifiers, a self-cut-off comparator, and a dual-supply DAC.

A DC-to-1 GHz Tunable RF $\Delta \Sigma$ ADC Achieving DR $ =$ 74 dB and BW $ =$ 150 MHz at $f_{0} =$ 450 MHz Using 550 mW

The ultimate ADC for receiver applications would be one that converts any desired RF signal directly into digital form so that the rest of the signal chain enjoys accurate and flexible digital signal processing and CMOS scaling. Flexibility in center frequency (f 0 ), bandwidth (BW), sampling frequency (f S ), full-scale (FS), dynamic range (DR) and power consumption (P) would allow the ADC to handle multiple standards and adapt to the RF environment [1–4]. The ADC reported in this paper is a step toward this Holy Grail of ADCs, supporting f 0 = 0 to 1GHz, BW = 35 to 150MHz, f S = 2 to 4GHz and FS = −18dBm to +18dBm. At f 0 = 450MHz, BW = 150MHz, f S = 4GHz and FS = +6dBm, the ADC achieves instantaneous DR = 74dB and peak SNR = 69dB with P = 550mW.

A DC-to-1GHz tunable RF ΔΣ ADC achieving DR = 74dB and BW = 150MHz at f 0 = 450MHz using 550mW

A second-order multi-bit quadrature bandpass continuous-time delta-sigma modulator (QBP-CTDSM) employing a power-scaling technique (PST) and a quadrature mismatch scrambler (QMS) for a tri-mode GSM-EDGE/UMTS/DVB-T low-IF receiver is reported in this paper. This modulator employs operational amplifiers with PST to optimize power consumption among the tri-mode operation. In addition, the modulator incorporates the proposed QMS to mitigate the mismatch between the I/Q multi-bit DACs. Fabricated in a 0.18-μm CMOS process, the proposed QBP-CTDSM achieves 81/61.2/60.9 dB SNDR across 270- kHz/5-MHz/8-MHz bandwidth. The bandpass center frequency is programmable from 500 kHz to 12 MHz. Measured from a 1.8-V supply voltage, the modulator power consumptions are 4.9/8.9/12.1 mW for the GSM-EDGE/UMTS/DVB-T modes, respectively, which result in FOMs of 0.99/0.95/0.84 pJ/conversion. The measurement results also show that the QBP-CTDSM achieves image rejection ratios better than 55 dB for all modes.

A Quadrature Bandpass Continuous-Time Delta-Sigma Modulator for a Tri-Mode GSM-EDGE/UMTS/DVB-T Receiver

A 1-0 MASH ΣΔ analog-to-digital converter (ADC) demonstrates a digital linearization technique for the first time treating integrator distortion with memory and capacitor mismatch errors. A two-tap sequential polynomial derived from an output-referred error analysis accurately models the non-ideality of a first-order modulator. The model parameters are extracted by correlating various moments of the ADC digital output with a one-bit pseudorandom noise (PN) superimposed on the input, largely reducing the circuit overhead associated with the nonlinear calibration. The prototype ADC employing amplifiers with a gain of roughly 30 dB measures an 85-dBc spurious-free dynamic range (SFDR) and a 67-dB signal-to-noise and distortion ratio (SNDR) for a 1.1- VPP ( -1-dBFS), 4.99-MHz sinusoidal input at 240 MHz sampling clock (8× OSR) with a 7.5-msec calibration time. For a 1.1- VPP two-tone input at 14.9 MHz and 15.1 MHz, the third-order intermodulation product (IM3) after calibration is 87.1 dBc, which is over 30 dB better than that without calibration. The core ADC consumes 37 mW from a 1.25-V supply and occupies 0.28 mm 2 in a 65-nm CMOS low-leakage digital process in which the transistor threshold voltages are around 0.5 V.

A 15-MHz Bandwidth 1-0 MASH $\Sigma \Delta $ ADC With Nonlinear Memory Error Calibration Achieving 85-dBc SFDR

A dynamic comparator-based OTA is introduced as a replacement for a conventional OTA. It performs charge transfer in a switched-capacitor circuit by repeatedly evaluating the polarity of the differential input using a dynamic clocked comparator and injecting current pulses at the output to move the input voltage toward zero. The amplitude of the current pulse is reduced each time the input voltage crosses zero to provide fast but accurate settling of the output voltage. Dynamic comparator-based OTAs are applied to the design of a 1-1-1-1 MASH delta-sigma modulator. The 65-nm CMOS prototype achieves a 70.4 dB peak SNDR over a 2.5-MHz bandwidth while consuming 3.73 mW from a 1.2-V supply. The 276-fJ/conv-step FoM represents a four times improvement over previously-reported delta-sigma modulators using zero-crossing-based circuits or comparator-based switched capacitors. Because of the dynamic operation of the OTAs and discrete-time delta-sigma modulator architecture, both bandwidth and power consumption linearly scale with the sampling frequency without any reconfiguration of the modulator.

A 1-1-1-1 MASH delta-sigma modulator using dynamic comparator-based OTAs

In this paper, analysis and design of a four-bit fourth- order delta-sigma modulator with a widely programmable center frequency are presented. Novel methods for quantizing and implementing the digitally programmable modulator coefficients enable performance comparable to state-of-the-art discrete-time fixed- frequency modulators at any center frequency from DC to 0.31 fs in steps of 0.0052 fs. The 0.18 mum 1.8 V CMOS prototype implemented in a silicon area of 4.5 mm 2 consumes 115 mW at a sampling frequency of 40 MHz. The SNDR and SNR over a 310 kHz bandwidth range from 71 dB to 82 dB and from 76 dB to 86 dB, respectively.

A Delta-Sigma Modulator With a Widely Programmable Center Frequency and 82-dB Peak SNDR

A. 4-bit fourth-order delta-sigma modulator with a widely programmable center frequency is presented. Novel methods for quantizing and implementing the digitally programmable modulator coefficients enable performance comparable to state-of-the-art discrete-time fixed-frequency modulators at any center frequency from dc to 0.31 fs in steps of 0.0052/s. The 0.18-mum 1.8-V CMOS prototype consumes 115 mW at a sampling frequency of 40 MHz. The peak SNDR and SNR over a 310-kHz bandwidth are 82 dB and 86 dB respectively.

/pdf/a-delta-sigma-modulator-with-a-widely-programmable-center-1jnbeoed25.pdf

K. Yamamoto

Papers

A 1-1-1-1 MASH delta-sigma modulator using dynamic comparator-based OTAs

A Delta-Sigma Modulator With a Widely Programmable Center Frequency and 82-dB Peak SNDR

A Delta-Sigma Modulator with a Widely Programmable Center Frequency and 82-dB Peak SNDR