A cellular floating-point serial pipelined multiplier arranged to accept two synchronous digit serial data streams in floating-point format and output one identically formatted stream which is the floating-point product of the synchronous input members, comprising a delay circuit (1) for the X operand and a digit re-ordering/delay circuit (2) for the Y operand connected to a pipelined addition circuit (3) which outputs the product through a delay cell (6), a MODE control signal propagation and generation circuit (4) connected to the pipelined addition circuit (3) and to the digit re-ordering/delay circuit (2), and a cell differentiation circuit (5) connected to control the pipelined addition circuit (3) and the digit re-ordering/delay circuit (2) and the X operand delay circuit (1).

A cellular floating-point serial-pipelined multiplier.

A multiplier for least significant bit first multiplication of a multiplicand coded on n bits by a multiplier coefficient includes a processor which, for each bit of the decimal part of the multiplier coefficient between the least significant bit and the most significant bit, calculates the sum of rank n+1 obtained from partial products of the bit in question with the n bits of the multiplicand and from corresponding sums calculated for the preceding bit or bits of the multiplier coefficient. This prevents internal overflow of the multiplier.

Multiplier, especially a serial bit multiplier, free from internal overflow, and method for preventing internal overflow in a multiplier

Un multiplicateur cellulaire pipeline en serie a virgule flottante accepte deux flux de donnees serielles numeriques synchrones ayant un format a virgule flottante et sort un flux de format identique qui est le produit a virgule flottante des elements synchrones d'entree, comprend un circuit de temporisation (1) pour l'operande X et un circuit de temporisation et de remise en ordre numerique pour l'operande Y connecte a un circuit pipeline d'addition (3) qui sort le produit par une cellule de temporisation (6), un circuit (4) de generation et de propagation de signaux de commande du MODE connecte au circuit pipeline d'addition (3) et au circuit de temporisation/remise en orde numerique, et un circuit de differentiation de position (5) connecte de maniere a commander le circuit pipeline d'addition (3), le circuit de temporisation/remise en ordre numerique (2) et le circuit de temporisation (1) de l'operande X.

Multiplicateur cellulaire pipeline en serie a virgule flottante

The multiplier, which is able to perform the leading low-order binary multiplication of a multiplicand coded on n bits with a multiplier coefficient, comprises processing means (14, 15, 16, 17, 19, 20) which are able, for each bit of the decimal part of the multiplier coefficient situated between the low-order bit and the high-order bit, actually to calculate the sum of rank n + 1 obtained from the partial products of the said relevant bit with the n bits of the multiplicand, and from the corresponding sums calculated for the preceding bit(s) of the multiplier coefficient, so as to avoid any internal overflow of the multiplier.

Bit-serial multiplier exempt from internal overflow.

Multiplieur exempt de débordement interne, notamment multiplieur bit-série, et procédé pour empêcher un débordement interne d'un multiplieur.

Serial two's complement pipeline multipliers are the basic module in the serial arithmetic implementation of digital signal processing algorithms. These multipliers accept the data serially in two's complement notation and generate a serial output product in two's complement notation as well. The designs, however, presented up to now lack in modularity; in addition, they have the problem of the internal overflow. In this paper a new two's complement multiplication algorithm is worked out, that allows cellular implementation of serial-pipeline multipliers and does not limit the dynamic range of the data input. In addition, by using the proposed cell, useful functions for digital signal processing can be performed. Methods are proposed for overflow detection, and comparison is made with previously proposed realizations.

K.Z. Pekmestzi

Papers

Cellular two's complement serial-pipeline multipliers