A new dielectric isolation technology is proposed. In the new structure, single crystalline Si islands are separated from the silicon substrate by oxidized porous silicon. It is based on the following characteristics of the porous silicon oxide formation: (1) p -type Si is more easily changed to porous silicon than n -type Si; (2) porous silicon is formed along the anodic reaction current flow line; (3) the change in volume of porous silicon after oxidation is relatively small; (4) thick porous silicon films (10 μm) can be obtained easily. In this method, a p -type isolated layer is obtained by proton implantation used for an n -type layer formation. Lateral p - n junctions fabricated in such isolated silicon layers show lower leakage current than those reported in SOS technology.

A new dielectric isolation method using porous silicon

It is well known that impurities and defects in semiconductors are associated with energy levels in the forbidden gap. Similar states occur at the surface of a semiconductor where the crystal lattice and the symmetry are strongly disturbed. These states are called surface states. Owing to the two-dimensional nature of the surface, their density is measured per unit area, in contrast to bulk states, which are measured per unit volume. A third type of states, similar to surface states, occurs at the interface between two adjacent materials. These states are called interface states. Very often they are also simply called surface states.

Interface states on semiconductor/insulator surfaces

An important aspect of the large expansion in the development and production of solid-state devices has been the demand for more sophisticated techniques for determining the electrical properties of semiconductors, especially silicon and the III-V compounds. A very wide range of measurement techniques now exists and it is the purpose of this article to review those techniques which are in widespread use or which show promise for future application, and at a time for continuing innovation in this area, to indicate present trends and material problems which may arise in the near future.

https://iopscience.iop.org/article/10.1088/0034-4885/41/2/001/pdf

The electrical characterisation of semiconductors

Publisher Summary This chapter highlights noise as a measure of quality and reliability in electronic devices The chapter attempts to describe what mechanisms have been well established as a source of noise related to the defective or nonideal nature of electronic devices This chapter is devoted to an account of the success that has been obtained in using noise as a nondestructive indicator of reliability The chapter is mainly concerned with a review of the properties of noise and some of the general principles behind the specific mechanisms Noise arises from many possible defects so that monitoring this single quantity can detect the presence of one or more of many different defects It is, therefore, necessary to be careful in interpreting noise results to ensure that a correct mechanism is assigned to the noise, and even greater care is necessary in comparing noise results among different specimens, because the origins and characteristics of the noises may be completely different As many of the detailed mechanisms for the production of the excess noise are becoming understood, the use of noise as an analysis quantity can increase

Electrical Noise as a Measure of Quality and Reliability in Electronic Devices

This paper presents accurate device models (1-3 percent) to describe the I_{D}-V_{D} electrical characteristics of surface-channel PMOS transistors in strong inversion, and ion-implanted depletion-mode buried-channel PMOS transistors. The primary emphasis is an accurate description of the transverse carrier mobility with distance and normal electrical field in long-channel structures. The influence of substrate bias on carrier mobility in the surface-channel device is modeled theoretically and verified by experiment. The carrier mobility in the buried-channel devices is constant as determined experimentally with gated-diode C-V and conductance measurements. The modeling parameters are determined at V_{D} = 0 with an automated data-acquisition micro-processor-controlled system. The models are analyzed with a least squares estimation criterion and a high degree of internal consistency is apparent from the statistical significance of the results.

High-accuracy MOS models for computer-aided design

A new method has been developed by which the doping profile of the semiconductor can be obtained right up to its surface. Contrary to the well known dC/dV-method, which is valid only in the depletion range, we have considered the majority carriers in deriving relations for doping density as well as distance from the semiconductor surface, in terms of the space charge capacitance and its derivative with respect to the surface potential. This method can be realized experimentally on any MIS structure. Measurements on MOS capacitors with steam grown oxides showed a drooping profile towards the SiSiO2 interface for boron doped and a rising one for phosphorus doped silicon. Post-oxidation annealing in dry nitrogen at 1200°C produced a uniform profile for phosphorus doped silicon.

K. Ziegler

Papers

Determination of the semiconductor doping profile right up to its surface using the MIS capacitor