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Showing papers by "Kai Li published in 2003"


Proceedings Article
01 Jan 2003
TL;DR: This paper presents an eviction-based placement policy for a storage cache that usually sits in the lower level of a multi-level buffer cache hierarchy and thereby has different access patterns from upper levels, and presents a method of using a client content tracking table to obtain eviction information from client buffer caches.
Abstract: Most previous work on buffer cache management uses an access-based placement policy that places a data block into a buffer cache at the block’s access time. This paper presents an eviction-based placement policy for a storage cache that usually sits in the lower level of a multi-level buffer cache hierarchy and thereby has different access patterns from upper levels. The main idea of the eviction-based placement policy is to delay a block’s placement in the cache until it is evicted from the upper level. This paper also presents a method of using a client content tracking table to obtain eviction information from client buffer caches, which can avoid modifying client application source code. We have evaluated the performance of this eviction-based placement by using both simulations with real-world workloads, and implementations on a storage system connected to a Microsoft SQL server database. Our simulation results show that the eviction-based cache placement has an up to 500% improvement on cache hit ratios over the commonly used access-based placement policy. Our evaluation results using OLTP workloads have demonstrated that the eviction-based cache placement has a speedup of 1.2 on OLTP transaction rates.

94 citations


Proceedings ArticleDOI
22 May 2003
TL;DR: A non-parametric full-gamut color matching algorithm that can achieve good color balance with 1.47% variance between projectors and a method for applying this color gamut mapping in real-time on the newest commodity graphics cards.
Abstract: This paper presents a non-parametric full-gamut color matching algorithm. Color matching is important for the seamless appearance of tiled displays. In particular we address the case where the tiled display is composed of different types of projectors or DLP projectors with white enhancement. White enhancement produces a non-additive color space that is difficult to model. We perform our calibration using an inexpensive colorimeter as opposed to a highly accurate spectroradiometer. Our results show that we can achieve good color balance with 1.47% variance between projectors. We present a method for applying this color gamut mapping in real-time on the newest commodity graphics cards.

64 citations


Proceedings Article
09 Jun 2003
TL;DR: The third edition of the ISCA Symposium on Computer Architecture as discussed by the authors was held in San Diego, California, USA, from January 18-21, 2003, with a focus on subsetting the SPEC benchmark suite.
Abstract: Welcome to San Diego, to ISCA'03, and to the Fourth Federated Computing Research Conference! It has been a pleasure to serve as Symposium Chairman, chiefly due to the opportunity to work with the volunteers and staff members mentioned below. I trust you will agree that the result of their efforts is again a conferences to be proud of, one that you are pleased to be attending. In addition to ISCA itself, I encourage you to take advantage of the FCRC activities, for example. the morning plenaries and the common breakfasts and lunches. If you can stay late Wednesday, I suggest the joint ISCA/SIGMETRICS workshop on Self-Managing Systems and if you stay longer, I recommend attending other FCRC constituent conferences.ISCA is widely regarded as the conference on computer architecture and the program committee has ensured that the 2003 symposium will be no exception. I am confident you will agree that the committee, under Kai Li's leadership, has once again put together a program of the highest technical excellence. Of course this excellence begins with first class submissions and this year's authors are to be congratulated on their successful efforts. This year, we were fortunate to receive financial support from IEEE Micro and Intel for our provocative panel on subsetting the SPEC benchmark suite.We used a conference review package, which was used by several program committees in computer architecture, to process the reviews. I would like to thank Dirk Grunwald for his initial development of the package and for his continuous help throughput the review process. Christine Lv served as our webmaster. She implemented several extensions to the package and her efficiency, patience and dedication greatly help the entire review process.The program committee reviewed the submissions carefully through the whole process. We continued the tradition of blind review process. Program committee members learned about the authors only at the time of the program committee meeting. Each paper was assigned to five program committee members, of which three served as primary and two served as secondary. The primary members reviewed the paper, while the secondary members were responsible for getting external reviews. We adopted the rebuttal process that used last year. The authors were given three days to respond to the initial reviews before the program committee meeting. We found the rebuttal process not only helped the program committee to clarify issues, but also set an early deadline for the reviewers to complete their reviews. The program committee met in Princeton on January 18, 2003. All committee members were provided with accesses to all reviews and numerical scores for all non-committee-authored papers. In general, we processed papers in the order of their rankings, but we only used the rankings as a guide. One of the primary program committee members acted as a lead to present the reviews and the authors' responses to the entire the program committee at the program committee meeting. The decision on each paper was made only after all program committee members who had read it expressed their opinions to the program committee and only after the program committee reached a consensus. Papers co-authored by program committee papers were handled in special sessions where the authors were not present. The committee accepted 8 out of 26 committee-authored papers. In the end, the program committee accepted 36 papers for the conference and one position paper for the panel "Subsetting SPEC when measuring results: valid or manipulative?" For three of the papers, a program committee member was asked to "shepherd" the revision process. The result is an excellent program you find in the proceedings.

7 citations


01 Jan 2003
TL;DR: This dissertation presents a framework for decoding and displaying ultra-high resolution videos on a scalable multi-projector tiled display system driven by a PC cluster, and proposes a classification of three kinds of scalable resolution videos for tiled displays.
Abstract: Video is a powerful means for people to communicate with each other across space and time. Its effectiveness is largely dependent on resolution and scale. Unlike most other information technologies, video resolution was increasing slowly during the past two decades. One of the major limiting factors was display resolution, which has been improving only at a rate of about 5% per year, while processor performance, memory density, network bandwidth and disk storage capacity are doubling every 18 to 24 months as predicted by Moore's Law. To overcome the resolution limit, researchers have recently proposed ways to construct multi-projector tiled display systems driven by commodity PC clusters. However, ultra-high resolution videos have not been available on such displays for several reasons. First, video resolution has been limited to the HDTV standard. Second, it has been difficult to parallelize MPEG video decoders to run on a cluster due to limited communication performance in the typical architecture. Third, to appear seamless, ultra-high resolution videos require accurate projector calibration, which is difficult to achieve on large-scale tiled displays. This dissertation presents a framework for decoding and displaying ultra-high resolution videos on a scalable multi-projector tiled display system driven by a PC cluster. It proposes a classification of three kinds of scalable resolution videos for tiled displays. First, a single ultra-high resolution video can be used for applications such as digital cinema or planetarium. Second, in remote scientific visualization, multiple low-resolution videos can be tiled to create scalable video resolution. Third, for immersive tele-presence applications, a high-resolution video can be formed by overlaying multiple low-resolution videos with different fields of view. Towards realizing this framework, this dissertation presents the design, implementation and evaluation of several key components necessary for building a scalable MPEG decoding system for tiled displays. The first component, a high-performance software MPEG video decoder, is used as the underlying building block for the scalable decoding system. Secondly, we propose a hierarchical parallel algorithm to decode and display ultra-high resolution MPEG streams on a PC cluster. Finally, sub-pixel accurate projector alignment is achieved with the camera homography tree algorithm; improved color consistency is attained using a new full-gamut color matching system. With these implementations, the system is able to accomplish a demanding task—it plays an IMAX quality, 3840 by 2800 pixel video at about 39 frames per second on a tiled display driven by a cluster of 21 PCs.

7 citations


Patent
28 Jan 2003
TL;DR: A disk-based archival storage system as mentioned in this paper includes a storage unit, including at least one spindle of disks to magnetically store archival data, and an interconnect to either archive to or retrieve data from the storage unit.
Abstract: A disk-based archival storage system (20) including a storage unit (26) configured to store archival data, including at least one spindle of disks to magnetically store archival data, an interconnect (24) to either archive to or retrieve data from the storage unit. In one embodiment, the system includes a plurality of the storage units each including at least one spindle of disks. The control unit (22) controls the storage commands to selectively cause the storage unit(s) to shut down or power up, enter a running mode or a standby mode, cause the spindle of disk(s) to either spin up or spin down, and to perform a data integrity check of all the archival data stored in the storage system. In various other embodiments, the control unit runs algorithms that expand the lifetime and longevity of the disk spindles, optimizes power consumption, and performs data migration when a data integrity check identifies correctable errors.

3 citations