Core-shell germanium nanowire (GeNW) is formed with a single-crystalline Ge core and concentric shells of nitride and silicon passivation layer by chemical vapor deposition (CVD), an Al2O3 gate dielectric layer by atomic layer deposition (ALD) and an Al metal surround-gate (SG) shell by isotropic magnetron sputter deposition. Surround gate nanowire field effect transistors (FETs) are then constructed using a novel self-aligned fabrication approach. Individual SG GeNW FETs show improved switching over GeNW FETs with planar gate stacks owing to improved electrostatics. FET devices comprised of multiple quasi-aligned SG GeNWs in parallel are also constructed. Collectively, tens of SG GeNWs afford on-currents exceeding 0.1mA at low source-drain bias voltages. The self-aligned surround gate scheme can be generalized to various semiconductor nanowire materials.

Parallel Core-Shell Metal-Dielectric-Semiconductor Germanium Nanowires for High Current Surround Gate Field Effect Transistors

Strained Ge p-channel FinFETs on Strain Relaxed SiGe are integrated for the first time on high density 45nm Fin pitch using a replacement channel approach on Si substrate. In comparison to our previous work on isolated sGe FinFETs [1], 14/16nm technology node compatible modules such as replacement metal gate and germanide-free local interconnect were implemented. The I ON /I OFF benchmark shows the high density strained Ge p-FinFETs in this work outperform the best published isolated strained Ge on SiGe devices.

Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

In this paper, we have successfully demonstrated high quality Extremely-thin body (ETB) Ge-on-insulator (GOI) p-MOSFETs with thickness ranging from 25 nm to 2 nm. Furthermore, the hole mobility and the GOI thickness dependence over a wide range of GOI thickness down to 2 nm are systematically analyzed and understood from the viewpoint of the scattering mechanisms, for the first time.

Experimental study on carrier transport properties in extremely-thin body Ge-on-insulator (GOI) p-MOSFETs with GOI thickness down to 2 nm

Ti/p-Ge and NiGe/p-Ge contacts are compared on both planar- and fin-based devices. Ti/p-Ge contacts show low contact resistance, while NiGe/p-Ge devices show short circuit problems due to thermally driven Ni diffusion. Considering the thermal budget in the standard backend of line processing for CMOS, Ti is more suitable for p-Ge devices. A low Ti/p-Ge contact resistivity of $1.1\times 10^{-8}~\Omega \cdot \textrm {cm}^{2}$ is achieved by using a multi-pulse laser annealing technique for B activation.

Low-Resistance Titanium Contacts and Thermally Unstable Nickel Germanide Contacts on p-Type Germanium

One of the key challenges in scaling beyond 10-nm technology node is device-to-device variation. Variation in device performance, mainly threshold voltage, $V_{T}$ , inhibits $V_{\rm CC}$ scaling. In this paper, we present a comprehensive study of process variations and sidewall roughness (SWR) effects in silicon (Si) bulk n-/p-FinFETs, In0.53Ga0.47As bulk n-FinFETs, germanium (Ge) bulk p-FinFETs, and gallium antimonide–indium arsenide (GaSb–InAs) staggered-gap heterojunction n-/p-tunnel FETs (HTFETs) using 3-D Technology Computer Aided Design numerical simulations. According to the sensitivity study, FinFET and tunnel FET (TFET) device parameters are highly susceptible to fin width, $W_{\rm FIN}$ , and ultrathin body thickness, $T_{b}$ , variations, respectively. TFETs show higher variation in device performance than FinFETs. A Monte Carlo study of SWR variation on n- and p-FinFETs shows higher $3\sigma \!(V_{T\,{\rm Lin}}$ ) of In0.53Ga0.47As bulk n- and Ge bulk p-FinFETs than their Si counterparts. Furthermore, to study the variation impact on memory circuits, we simulate 6T and 10T static random access memory (SRAM) cells with FinFETs and HTFETs, respectively. The probability distribution of read failure in SRAM cells at different supply voltages, $V_{\rm CC}$ , shows that HTFETs require 10T SRAM cell architecture and less than 4% variation in $T_{b}$ for their $V_{\rm CCmin}$ to approach 200 mV.

Impact of Variation in Nanoscale Silicon and Non-Silicon FinFETs and Tunnel FETs on Device and SRAM Performance

We report scaled Ge p-channel FinFETs fabricated on a 300-mm Si wafer using the aspect-ratio-trapping technique. For long-channel devices, a combination of a trap-assisted tunneling and a band-to-band tunneling leakage mechanism is responsible for an elevated bulk current limiting the OFF-state drain current. However, the latter can be mitigated by device design. We report low long-channel subthreshold swing of 76 mV/decade at VDS=-0.5 V, good short-channel effect control, and high transconductance (gm=1.2 mS/μm at VDS=-1 V and 1.05 mS/μm at VDS=-0.5 V for LG=70 nm). The Ge FinFET presented in this paper exhibits the highest gm/SSsat at VDD=1 V reported for nonplanar unstrained Ge p-FETs to date.

Kai-Min Yin

Papers

Germanium p-Channel FinFET Fabricated by Aspect Ratio Trapping