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Design Of Analog Cmos Integrated Circuits

A time-interleaved multichannel analog-to-digital converter (ADC) achieves high sampling rates with the drawback of additional distortions caused by channel mismatches. In this paper, we consider the dependency of the signal-to-noise-and-distortion ratio (SINAD) on the combination of several different channel mismatch effects. By using either explicitly given mismatch parameters or given parameter distributions, we derive closed-form equations for calculating the explicit or the expected SINAD for an arbitrary number of channels. Furthermore, we extend the explicit SINAD by the impact of timing jitter. We clarify how channel mismatches interact and perform a worst case analysis of the explicit SINAD for individual mismatch errors. We also show that equations describing the expected SINAD of individual mismatch errors are special cases of our general formulation. We indicate how to use the expected SINAD for finding efficient optimization priorities and demonstrate the importance of worst case analyses.

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The impact of combined channel mismatch effects in time-interleaved ADCs

This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

The immense increase in multimedia-on-demand traffic that refers to audio, video, and images, has drastically shifted the vision of the Internet of Things (IoT) from scalar to Multimedia Internet of Things (M-IoT). IoT devices are constrained in terms of energy, computing, size, and storage memory. Delay-sensitive and bandwidth-hungry multimedia applications over constrained IoT networks require revision of IoT architecture for M-IoT. This paper provides a comprehensive survey of M-IoT with an emphasis on architecture, protocols, and applications. This article starts by providing a horizontal overview of the IoT. Then, we discuss the issues considering the characteristics of multimedia and provide a summary of related M-IoT architectures. Various multimedia applications supported by IoT are surveyed, and numerous use cases related to road traffic management, security, industry, and health are illustrated to show how different M-IoT applications are revolutionizing human life. We explore the importance of Quality-of-Experience (QoE) and Quality-of-Service (QoS) for multimedia transmission over IoT. Moreover, we explore the limitations of IoT for multimedia computing and present the relationship between the M-IoT and emerging technologies including event processing, feature extraction, cloud computing, Fog/Edge computing and Software-Defined-Networks (SDNs). We also present the need for better routing and Physical-Medium Access Control (PHY-MAC) protocols for M-IoT. Finally, we present a detailed discussion on the open research issues and several potential research areas related to emerging multimedia communication in IoT.

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Multimedia Internet of Things: A Comprehensive Survey

In this paper, we propose a novel joint data-hiding and compression scheme for digital images using side match vector quantization (SMVQ) and image inpainting. The two functions of data hiding and image compression can be integrated into one single module seamlessly. On the sender side, except for the blocks in the leftmost and topmost of the image, each of the other residual blocks in raster-scanning order can be embedded with secret data and compressed simultaneously by SMVQ or image inpainting adaptively according to the current embedding bit. Vector quantization is also utilized for some complex blocks to control the visual distortion and error diffusion caused by the progressive compression. After segmenting the image compressed codes into a series of sections by the indicator bits, the receiver can achieve the extraction of secret bits and image decompression successfully according to the index values in the segmented sections. Experimental results demonstrate the effectiveness of the proposed scheme.

A Novel Joint Data-Hiding and Compression Scheme Based on SMVQ and Image Inpainting

This letter presents a new efficient architecture for high-speed advanced encryption standard (AES) encryptor. This technique is implemented using composite field arithmetic byte substitution, where higher efficiency is achieved by merging and location rearrangement of different operations required in the steps of encryption. The proposed architecture is presented with multistage subpipelined architecture that allows having higher efficiency in terms of (throughput/area) than any previous field-programmable gate array (FPGA) implementations.

High-Speed AES Encryptor With Efficient Merging Techniques

This paper presents a study on the applicability of using approximate multipliers to enhance the performance of the VGGNet deep learning network. Approximate multipliers are known to have reduced power, area, and delay with the cost of an inaccuracy in output. Improving the performance of the VGGNet in terms of power, area, and speed can be achieved by replacing exact multipliers with approximate multipliers as demonstrated in this paper. The simulation results show that approximate multiplication has a very little impact on the accuracy of VGGNet. However, using approximate multipliers can achieve significant performance gains. The simulation was completed using different generated error matrices that mimic the inaccuracy that approximate multipliers introduce to the data. The impact of various ranges of the mean relative error and the standard deviation was tested. The well-known data sets CIFAR-10 and CIFAR-100 were used for testing the network’s classification accuracy. The impact on the accuracy was assessed by simulating approximate multiplication in all the layers in the first set of tests, and in selective layers in the second set of tests. Using approximate multipliers in all the layers leads to very little impact on the network’s accuracy. In addition, an alternative approach is to use a hybrid of exact and approximate multipliers. In the hybrid approach, 39.14% of the deeper layer’s multiplications can be approximate while having a reduced negligible impact on the network’s accuracy.

Impact of Approximate Multipliers on VGG Deep Learning Network

A CMOS active inductor with thermal noise cancelling is proposed. The noise of the transistor in the feed-forward stage of the proposed architecture is cancelled by using a feedback stage with a degeneration resistor to reduce the noise contribution to the input. Simulation results using 90 nm CMOS process show that noise reduction by 80% has been achieved. The maximum resonant frequency and the quality factor obtained are 3.8 GHz and 405, respectively. An RF band-pass filter has been designed based on the proposed noise cancelling active inductor. Tuned at 3.46 GHz, the filter features total power consumption of 1.4 mW, low noise figure of 5 dB, and IIP3 of −10.29 dBm.

/pdf/noise-cancelling-cmos-active-inductor-and-its-application-in-3tgrjaewcp.pdf

Noise-Cancelling CMOS Active Inductor and Its Application in RF Band-Pass Filter Design

Efficient calibration of circuits is performed using injection imprecise voltage by using different voltages in a subtractive manner to be able to calibrate with respect to a voltage that is out of a desirable measurable range using measuring circuitry. Efficient background calibration of circuits is also achieved by providing an equivalent circuit element to circuit elements receiving an injected calibration signal, and switching circuit elements. Such imprecise voltages can be determined through such calibration, and then used to calibrate a second circuit generating the imprecise voltages.

Circuit calibration using voltage injection

High Efficiency Video Coding (HEVC) encryption, which has been proposed to encrypt intra prediction modes (structural information), transform coefficients (texture information), and motion related codewords (motion information), has received considerable attention recently. However, there is still the issue of efficiency when HEVC encryption is applied in the Internet of Multimedia Things (IoMT). Aiming at this challenge, in this paper, we propose a new low-overhead HEVC encryption scheme for energy-constrained IoMT. Concretely, the proposed scheme adjusts the selection of the aforementioned syntax elements to be encrypted according to the structure, texture, and motion energy present in each frame. It works as follows. The energy levels of quantized coefficients and motion vectors are calculated and compared with adaptive threshold values to classify the energy level in each video frame. When there is a high energy frame in the video, all the syntax elements are encrypted. When there is a low energy frame, alternate syntax elements are encrypted for achieving low encryption overhead. Moreover, in the case of transform coefficients, to withstand the interpolation attack, alternate coefficients are encrypted after correlating the frame with its neighboring coefficients. Extensive experiments were conducted, and the results demonstrate that the proposed scheme efficiently reduces the encryption overhead with low impact on the security level, making it suitable for IoMT.

Kamal El-Sankary

Papers

High-Speed AES Encryptor With Efficient Merging Techniques

Impact of Approximate Multipliers on VGG Deep Learning Network

Noise-Cancelling CMOS Active Inductor and Its Application in RF Band-Pass Filter Design

Circuit calibration using voltage injection

Energy-Aware Encryption for Securing Video Transmission in Internet of Multimedia Things