Methods and apparatus for power monitoring with sequencing and supervision are disclosed. An example method disclosed herein includes supervising a first power rail and a second power rail, sequencing a first enable signal associated with the first power rail and a second enable signal associated with the second power rail, and determining whether the first power rail is enabled based on regulation information determined while supervising the first power rail.

Supervising and sequencing commonly driven power supplies with digital information

A method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress. According to the invention, since a compression stress on the etched layer or the amorphous carbon film can be reduced or a compression stress film is formed between the etched layer or the amorphous carbon film to prevent a lifting phenomenon from occurring and thus another pattern can be formed to fabricate a highly integrated semiconductor device.

Method for Fabricating Semiconductor Device

An integrated circuit device includes: a RAM block including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block. The data line driver block includes first to Nth (N is an integer larger than one) divided data line driver blocks, each of the first to Nth divided data line driver blocks driving a different data line group of the data line groups. The wordline control circuit drives an identical wordline N times from among the wordlines in one horizontal scan period of the display panel. The first to Nth divided data line drivers are disposed along a first direction in which the bitlines extend.

Integrated circuit device and electronic instrument

Pipelined analog-to-digital converters (ADCs) tend to be sensitive to component mismatches in their internal digital-to-analog converters (DACs), The component mismatches give rise to error, referred to as DAC noise, which is not attenuated or cancelled along the pipeline as are other types of noise. This paper describes an all-digital technique that significantly mitigates this problem. The technique continuously measures and cancels the portion of the ADC error arising from DAC noise during normal operation of the ADC, so no special calibration signal or auto-calibration phase is required. The details of the technique are described in the context of a nominal 14-bit pipelined ADC example at both the signal processing and register transfer levels. Through this example, the paper demonstrates that in the presence of realistic component matching limitations the technique can improve the overall ADC accuracy by several bits with only moderate digital hardware complexity.

Digital cancellation of D/A converter noise in pipelined A/D converters

A state-based remote control system for providing efficient and simple operation of a plurality of electronic devices as a coordinated system based upon an overall task. The state-based remote control system includes a housing, a keypad in communication with an electronic system contained within the housing, and a communication device in communication with the electronic system for communicating with external electronic devices. The electronic system monitors the buttons selected by a user to determine the state of all external electronic devices that are to be controlled. When the user selects a task (e.g. watch television), the electronic system automatically determines the actions required to achieve the desired task based upon the current state of the external electronic devices. After the task has been fulfilled, the electronic system updates the data to reflect the modified state of the external electronic devices.

State-based remote control system

An analog-to-digital converter (ADC) integrated circuit includes a subconverter stage having an amplifier with a non-ideal gain, and a reference voltage generator for generating a reference voltage for the subconverter stage. The reference voltage generator is adjustable and may include trimmable resistors for providing an adjusted or trimmed reference voltage to a second subconverter stage or second operation of the subconverter stage to compensate for a non-ideal gain of the amplifier. Complicated and difficult capacitor trimming for the amplifier is not needed; rather, a relatively simple and predictable trimming of thin film resistors in the reference voltage generator may be used to compensate for the non-ideal gain of the amplifier and improve performance. A method and apparatus for calibrating the ADC are also disclosed.

Integrated circuit analog-to-digital converter and associated calibration method and apparatus

A two-step analog-to-digital converter (300) and BiCMOS fabrication method to make the converter. The fabrication method provides pseudosubstrate isolation of digital CMOS devices from analog devices. The converter uses NPN current switching in a flash analog-to-digital converter (306) and in a digital-to-analog converter (310) for low noise operation. CMOS digital error correction (318) and BiCMOS output drivers (320) provide high packing density plus large output load handling. Timing control (330) aggregates switching events and puts them into intervals when noise sensitive operations are inactive. The fabrication method uses a thin epitaxial layer with limited thermal processing to provide NPN and PNP devices with large breakdown and Early voltages. Laser trimmed resistors provide small-long term drift due to dopant stabilization in underlying BPSG and low hydrogen nitride passivation.

Analog-to-digital converter and method of fabrication

A digital-to-analog converter (DAC) includes a first array of current source cells extending in first and second transverse directions, and a two-dimensional symmetrical controller for operating current source cells of the first array based upon at least a portion of digital input words and in a symmetrical sequence in both the first and second directions with respect to a medial position of the first array. The medial position preferably defines a centroid for the first array. The two-dimensional symmetrical controller may preferably include a decoder for generating a plurality of control signals based upon predetermined most significant bits (MSBs) of digital input words. Another aspect of the invention relates to the treatment of the LSBs. According to this aspect, the first array further comprises a plurality of second current source cells, and the two-dimensional symmetrical controller further operates the plurality of second current source cells based upon predetermined LSBs of digital input words. The DAC may include a substantially identical second array adjacent the first array. The two-dimensional symmetrical controller may operate the current source cells in the first and second arrays in pairs and in a substantially mirror image sequence to provide geometrical averaging. The geometrical averaging may operate the current source cells in the first and second arrays in pairs and in a substantially true mirror or inverted mirror image sequence.

Digital-to-analog converter including current cell matrix with enhanced linearity and associated methods

A comparator 10 has a first stage differential amplifier 11 coupled to a second stage, single ended differential amplifier 12. The output of the second stage is coupled to a latch input stage 15 of a latch 16. A latch replica bias circuit 20 operates the second stage at a clamp voltage corresponding to the threshold voltage of latch 16. A clock signal clk switches the second stage 12 between gain and clamp modes.

High speed comparator

Then circuit includes an analog-to-digital converter (ADC); and one or more switched capacitor amplifier stages connected together in series with a first switched capacitor amplifier stage for receiving the analog input signal, and a last switched capacitor amplifier stage connected to the ADC. Moreover, each of the plurality of switched capacitor amplifier stages preferably has a selectable gain to permit control of an overall gain of the analog input signal upstream of the ADC. In addition, the first stage may also serve as a sample and hold circuit for the ADC. In one embodiment, the circuit may comprise an integrated circuit substrate on which the ADC and the plurality of switched capacitor amplifiers are formed so that the analog-to-digital converter is a monolithic integrated circuit. The circuit may also control the gain of each of the plurality of switched capacitor amplifier stages based upon a digital gain control word. A clock is preferably operatively connected to the ADC and the plurality of switched capacitor amplifier stages. Accordingly, gain control word changes cause relatively rapid changes in the overall gain.

Kantilal Bacrania

Papers

Integrated circuit analog-to-digital converter and associated calibration method and apparatus

Analog-to-digital converter and method of fabrication

Digital-to-analog converter including current cell matrix with enhanced linearity and associated methods

High speed comparator

Processor controlled analog-to-digital converter circuit