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Patent

Processor controlled analog-to-digital converter circuit

TLDR
In this article, an analog-to-digital converter (ADC) and one or more switched capacitor amplifier stages are connected together in series, with the first stage serving as a sample and hold circuit for the ADC.
Abstract
Then circuit includes an analog-to-digital converter (ADC); and one or more switched capacitor amplifier stages connected together in series with a first switched capacitor amplifier stage for receiving the analog input signal, and a last switched capacitor amplifier stage connected to the ADC. Moreover, each of the plurality of switched capacitor amplifier stages preferably has a selectable gain to permit control of an overall gain of the analog input signal upstream of the ADC. In addition, the first stage may also serve as a sample and hold circuit for the ADC. In one embodiment, the circuit may comprise an integrated circuit substrate on which the ADC and the plurality of switched capacitor amplifiers are formed so that the analog-to-digital converter is a monolithic integrated circuit. The circuit may also control the gain of each of the plurality of switched capacitor amplifier stages based upon a digital gain control word. A clock is preferably operatively connected to the ADC and the plurality of switched capacitor amplifier stages. Accordingly, gain control word changes cause relatively rapid changes in the overall gain.

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Citations
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Integrated circuit device and electronic instrument

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Journal ArticleDOI

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References
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Patent

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TL;DR: In this paper, a delta signma modulator is programmable to realize a number of different gain settings, such as selecting the rate of sampling of an analog input relative to sampling of a reference voltage and/or interspersing of samples of fixed voltage with the analog input or reference voltage.
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TL;DR: In this paper, a delta sigma analog-to-digital converter with programmable resolution/bias current control circuitry is described, where a clock generator is used to supply a clock signal to the input sampling circuit and a feedback sampling circuit at a sampling frequency determined by a sampling-frequency control signal.
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