We present the science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems, targeting an evolution in technology, that might lead to impacts and benefits reaching into most areas of society. This roadmap was developed within the framework of the European Graphene Flagship and outlines the main targets and research areas as best understood at the start of this ambitious project. We provide an overview of the key aspects of graphene and related materials (GRMs), ranging from fundamental research challenges to a variety of applications in a large number of sectors, highlighting the steps necessary to take GRMs from a state of raw potential to a point where they might revolutionize multiple industries. We also define an extensive list of acronyms in an effort to standardize the nomenclature in this emerging field.

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Science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems

Graphene is readily p-doped by adsorbates, but for device applications, it would be useful to access the n-doped material. Individual graphene nanoribbons were covalently functionalized by nitrogen species through high-power electrical joule heating in ammonia gas, leading to n-type electronic doping consistent with theory. The formation of the carbon-nitrogen bond should occur mostly at the edges of graphene where chemical reactivity is high. X-ray photoelectron spectroscopy and nanometer-scale secondary ion mass spectroscopy confirm the carbon-nitrogen species in graphene thermally annealed in ammonia. We fabricated an n-type graphene field-effect transistor that operates at room temperature.

https://science.sciencemag.org/content/sci/324/5928/768.full.pdf

N-doping of graphene through electrothermal reactions with ammonia.

N-doping of graphene through electrothermal reactions with ammonia (vol 324, pg 768, 2009)

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS2 represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS2. Our integrated circuits are capable of operating as inverters, converting logical “1” into logical “0”, with room-temperature voltage gain higher than 1, making them suitable for incorporat...

Integrated Circuits and Logic Operations Based on Single-Layer MoS2

Advances in memory compiler technology have helped accelerate the integration of hundreds of unique embedded memory macros in contemporary low-power, high-speed SoCs. The heavy use of compiled memories poses multiple challenges on the characterization, validation, and reliability fronts. This motivates solutions that can reduce overall cost, time, and risk to certify memories through the identification of a reduced set of 'fundamental' memory macros that can be used one or more times to realize all memory instances in the design. This paper describes MemPack, a fast, general method based upon the classical change-making algorithm for the identification of such fundamental memory macros. By relaxing the need for exact realization of memories and tolerating wastage within the context of change-making, MemPack enables tradeoffs between memory capacity and reduction in the number of fundamental macros. It also controls multiplexing and instantiation costs, minimizing the impact on critical path delay and address line loading. Results on industrial and synthetic benchmarks for three different optimization objectives (performance, balance, and minimization) show that MemPack is effective in identifying fundamental sets that are as much as 16x smaller than the original set for 0.8--4.7% wasted bits.

https://www.pitt.edu/~kmram/publications/IP5_08_0324.pdf

Mempack: an order of magnitude reduction in the cost, risk, and time for memory compiler certification

This paper describes a virtual two-port memory architecture for emerging asymmetric non-volatile memory technologies. Realized using only conventional single-port memory cells that provide excellent scalability and density, virtual two-porting delivers the speed and bandwidth of physical two-port memory for just 1.8% of the cost of physical two-porting. Performance analysis of the SPEC CPU2006 benchmarks show that the read (write) performance of the virtual two-port architecture is within 0.6% (1.1%) of physical two-port memory, and it reduces the read (write) latency by 48.4% (45.6%) over conventional single-port memory.

Kartik Mohanram

Papers

Mempack: an order of magnitude reduction in the cost, risk, and time for memory compiler certification

Virtual Two-Port Memory Architecture for Asymmetric Memory Technologies