We present the science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems, targeting an evolution in technology, that might lead to impacts and benefits reaching into most areas of society. This roadmap was developed within the framework of the European Graphene Flagship and outlines the main targets and research areas as best understood at the start of this ambitious project. We provide an overview of the key aspects of graphene and related materials (GRMs), ranging from fundamental research challenges to a variety of applications in a large number of sectors, highlighting the steps necessary to take GRMs from a state of raw potential to a point where they might revolutionize multiple industries. We also define an extensive list of acronyms in an effort to standardize the nomenclature in this emerging field.

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Science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems

Graphene is readily p-doped by adsorbates, but for device applications, it would be useful to access the n-doped material. Individual graphene nanoribbons were covalently functionalized by nitrogen species through high-power electrical joule heating in ammonia gas, leading to n-type electronic doping consistent with theory. The formation of the carbon-nitrogen bond should occur mostly at the edges of graphene where chemical reactivity is high. X-ray photoelectron spectroscopy and nanometer-scale secondary ion mass spectroscopy confirm the carbon-nitrogen species in graphene thermally annealed in ammonia. We fabricated an n-type graphene field-effect transistor that operates at room temperature.

https://science.sciencemag.org/content/sci/324/5928/768.full.pdf

N-doping of graphene through electrothermal reactions with ammonia.

N-doping of graphene through electrothermal reactions with ammonia (vol 324, pg 768, 2009)

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS2 represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS2. Our integrated circuits are capable of operating as inverters, converting logical “1” into logical “0”, with room-temperature voltage gain higher than 1, making them suitable for incorporat...

Integrated Circuits and Logic Operations Based on Single-Layer MoS2

This paper describes a write-once-memory-code phase change memory (WOM-code PCM) architecture for next-generation non-volatile memory applications. Specifically, we address the long latency of the write operation in PCM—attributed to PCM SET—by proposing a novel PCM memory architecture that integrates the $\langle 2^2\rangle ^2/3$ WOM-code at the memory organization and memory controller levels. To further improve the write latency of WOM-code PCM, we propose a PCM-refresh approach that uses idle cycles to preemptively set PCM rows to the initial WOM-code state. Finally, to balance write latency improvements against WOM-code PCM overhead, we propose a WOM-code cached PCM (WCPCM) architecture that uses WOM-code PCM as the cache alongside conventional PCM main memory. Since WOM-code techniques inherently impact PCM endurance by increasing the number of bit-writes in comparison to unencoded PCM, we incorporate additional transitions from the $\langle 2^2\rangle ^2/3$ WOM-code transition graph to realize endurance-WOM-code (e-WOM-code) architectures. Transitions between the e-WOM-code states on writes to memory are integrated into an incremental coding for endurance (ICE) approach that exploits redundancies in the conventional WOM-code to reduce the number of bit-writes over unencoded PCM. Simulation results show that the proposed e-WOM-code PCM architecture is able to reduce memory write (read) latency by 19.8 percent (14.7 percent) and the number of bit-writes over unencoded PCM without (with) data-comparison write (DCW), a read-modify-write process that only updates changed cells, by 83.0 percent (22.1 percent) on average across general-purpose (SPEC CPU2006), embedded (MiBench), and high-performance (SPLASH-2) benchmarks. Further, e-WOM-code PCM with PCM-refresh can reduce memory write (read) latency by 51.5 percent (44.1 percent) and the number of bit-writes over unencoded PCM without DCW by 76.5 percent on average across the benchmarks; there is, however, an increase of 19 percent in the number of bit-writes over unencoded PCM with DCW. Finally, for just 4.7 percent memory overhead, the e-WOM-code cached PCM (e-WCPCM) architecture reduces memory write (read) latency by 47.5 percent (41.6 percent) and the number of bit-writes over unencoded PCM without DCW by 68.1 percent on average across the benchmarks; again, there is a 49 percent increase in the number of bit-writes over unencoded PCM with DCW.

WOM-Code Solutions for Low Latency and High Endurance in Phase Change Memory

This paper describes a tunable transient filter (TTF) design for soft error rate reduction in combinational logic circuits. TTFs can be inserted into combinational circuits to suppress propagated single-event transients (SETs) before they can be captured in latches or flip-flops. TTFs are tuned by adjusting the maximum width of the propagated SET that can be suppressed. A TTF requires 6–14 transistors, making it an attractive cost-effective option to reduce the soft error rate in combinational circuits. A global optimization approach based on geometric programming that integrates TTF insertion with dual-V DD and gate sizing is described. Simulation results for the 65 nm process technology indicate that a 17–48× reduction in the soft error rate can be achieved with this approach.

Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion

This paper presents a novel design-for-test (DFT) technique that allows core vendors to reduce the test complexity of a core they are trying to market. The idea is to design a core so that it can be tested with a very small number of test vectors. The I/O pins of such a "designed for high test compression" (DFHTC) core are identical to the I/O pins of an ordinary core. For the system integrator, testing a DFHTC core is identical to testing an ordinary core. The only difference is that the DFHTC core has a significantly smaller number of test vectors resulting in less test data as well as less test time (fewer scan vectors). This is achieved by carefully combining a parallel "test per clock" BIST scheme inside the core with the normal external testing scheme using a tester. The BIST structure inside the core generates weighted pseudo-random test vectors which detect a large number of faults in the core. Results indicate that such DFHTC cores have a significantly smaller number of test vectors than their ordinary counterparts thereby greatly reducing test time and test storage.

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An embedded core DFT scheme to obtain highly compressed test sets

In this paper, we introduce unequal-error-protection error correcting codes (UEPECCs) to improve SRAM reliability at low supply voltages for mobile multimedia applications. The fundamental premise for our work is that in multimedia applications, different bits in the same SRAM word are usually not equally significant, and hence deserve different protection levels. The key innovation in our work includes (i) a novel metric, word mean squared error, to measure the reliability of a SRAM word when different bits are not equally significant and (ii) an optimization algorithm based on dynamic programming to construct the UEPECC that assigns different protection levels to bits according to their significance. The advantage of the UEPECC over the traditional equal-error-protection ECC is demonstrated using two representative multimedia applications. For the same area, power, and encoding/decoding latency, SRAMs with UEPECC increase the peak signal-to-noise ratio by 8 dB in image processing and incur 60% less errors on average in optical flow (motion vector) computation.

Unequal-error-protection codes in SRAMs for mobile multimedia applications

Modern computing systems that integrate emerging non-volatile memories (NVMs) are vulnerable to classical security threats to data confidentiality (e.g., stolen DIMM and bus snooping attacks) as well as new security threats to system availability (e.g., denial of memory service (DoMS) attacks). Although counter mode encryption (CME) secures NVM-based main memories against confidentiality attacks, counter sizing is critical to balance tradeoffs between memory overhead, system performance, and re-encryption frequency (i.e., system availability). Furthermore, CME is particularly vulnerable to DoMS attacks, where a malicious application can severely impact memory availability by forcing frequent full memory re-encryption. This paper proposes Advanced Counter Mode Encryption, i.e., ACME, a low overhead CME-based main memory encryption solution to realize the twin security goals of confidentiality and availability in NVM-based main memories. At its core, ACME integrates counter write leveling (CWL) to reduce the frequency of full memory re-encryption while preserving the security properties of the underlying CME. Our evaluations on a phase change memory (PCM) architecture using SPEC CPU2006 benchmarks show that for a system availability of 99.999%, ACME not only requires 50% lower counter overhead, but also improves system performance by 20% in comparison to classical CME. When subject to a DoMS attack in the form of an unprivileged Linux process that sidesteps all levels of cache to constantly write to the same memory address to precipitate counter overflow, the ACME-based system provides 99.9% system availability in contrast to a classical CME-based system that is rendered non-operational.

https://dl.acm.org/doi/pdf/10.1145/3195970.3195983

Kartik Mohanram

Papers

WOM-Code Solutions for Low Latency and High Endurance in Phase Change Memory

Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion

An embedded core DFT scheme to obtain highly compressed test sets

Unequal-error-protection codes in SRAMs for mobile multimedia applications

ACME: advanced counter mode encryption for secure non-volatile memories