A lithographic apparatus configured to project a patterned beam of radiation onto a target portion of a substrate is disclosed. The apparatus includes a first radiation dose detector and a second radiation dose detector, each detector comprising a secondary electron emission surface configured to receive a radiation flux and to emit secondary electrons due to the receipt of the radiation flux, the first radiation dose detector located upstream with respect to the second radiation dose detector viewed with respect to a direction of radiation transmission, and a meter, connected to each detector, to detect a current or voltage resulting from the secondary electron emission from the respective electron emission surface.

Lithographic apparatus, and device manufacturing method

PROBLEM TO BE SOLVED: To prevent a resin protective film from being easily warped entirely in curing when forming the resin protective film for protecting bottom and side faces of a silicon substrate. SOLUTION: First, a first groove 28 is formed in a semiconductor wafer 21, a sealing film 12, and the like at a dicing street 22 and parts corresponding to both the sides of the dicing street 22. In this state, the semiconductor wafer 21 is separated into individual silicon substrates 1 by the formation of the first groove 28. Then, a resin protective film 11 is formed on the bottom face of the respective silicon substrates 1 including the inside of the first groove 28. In this case, although the semiconductor wafer 21 is separated into the individual silicon substrates 1, a first support plate 24 is stuck to an upper surface of a columnar electrode 10 and the sealing film 12 via a first adhesive layer 23, thus preventing an entire part including the individually separated silicon substrates 1 from being warped easily when forming the resin protective film 11. COPYRIGHT: (C)2010,JPO&INPIT

Method of manufacturing semiconductor device

A phase-shift mask having a checkerboard array and a surrounding sub-resolution assist phase pattern. The checkerboard array comprises alternating phase-shift regions R that have a relative phase difference of 180 degrees. The sub-resolution assist phase regions R′ reside adjacent corresponding phase-shift regions R and have a relative phase difference of 180 degrees thereto. The sub-resolution assist phase regions R′ are configured to mitigate undesirable edge effects when photolithographically forming photoresist features. Method of forming LEDs using the phase-shift mask are also disclosed.

Phase-shift mask with assist phase regions

Provided is an integrated circuit (IC) design method The method includes receiving an IC design layout having a feature with an outer boundary, performing a dissection on the feature to divide the outer boundary into a plurality of segments, and performing, using the segments, an optical proximity correction (OPC) on the feature to generate a modified outer boundary The method also includes simulating a photolithography exposure of the feature with the modified outer boundary to create a contour and performing an OPC evaluation to determine if the contour is within a threshold Additionally, the method includes repeating the performing a dissection, the performing an optical proximity correction, and the simulating if the contour does not meet the threshold, wherein each repeated dissection and each repeated optical proximity correction is performed on the modified outer boundary generated by the previously performed optical proximity correction

Method and apparatus for enhanced optical proximity correction

Systems and methods of semiconductor device fabrication and layout generation are disclosed. An exemplary method includes processes of depositing a layer of a first material and patterning the layer to form an initial pattern, wherein the initial pattern defines critical features of the layout elements using a single exposure; depositing spacer material over the first pattern on the substrate and etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of the first pattern; removing the initial pattern from the substrate while leaving the spacer material in a spacer pattern; filling the spacer pattern with final material; and trimming the tilled pattern to remove portions of the final material beyond dimensions of the layout elements.

Spacer double patterning for lithography operations

The main mask pattern of a photomask is corrected by adding serifs of one type (inner or outer) to a pair of mutually adjacent corners in the pattern, and adding a serif of the opposite type (outer or inner) to the edge between the corners. When the photomask is used to create a resist pattern by photolithography in the fabrication of a semiconductor device, the serifs combine to produce an optical proximity correction that reduces corner rounding and increases edge straightness in the resist pattern.

Mask pattern correction method

PROBLEM TO BE SOLVED: To prevent the occurrence of pattern defects due to focus deviation in an exposure process of photo etching by suppressing the global thickness variation of a substrate in manufacturing processes. SOLUTION: In this method of manufacturing a semiconductor device, a substrate 10 having an interconnection portion 11 and a light-receiving element portion 12 is used. In a process 1, a wiring pattern 14-1a is formed on the interconnection portion 11. In a process 2, a film to be polished 20-1 is stacked. In a process 3, the deposited film 20-1 is planarized by CMP. In a process 4, a plurality of holes are formed on the wiring pattern 14-1a in the planarized surfaces to be polished 20-1a and 20-1b, and these holes are filled with a conductor 22-1. By repeating the processes 1 to 4 n times, an n-layer interconnection is formed. In the xth repetition (1≤x≤n), a dummy pattern (for example, metal pattern) 23 for covering the whole surface of a light-receiving element 13 is formed. Thereafter, the metal pattern 23 is removed by etching to expose the light-receiving element 13. COPYRIGHT: (C)2009,JPO&INPIT

PROBLEM TO BE SOLVED: To provide a correction method for a mask pattern capable of correcting the mask pattern of a photomask, suppressing the shape degradation (rounding, especially) of the corner part of a resist pattern and bringing the resist pattern close to a desired pattern, and to provide the photomask, an exposure method and a semiconductor device. SOLUTION: In the correction method for the mask pattern, a desired main mask pattern is corrected and the shape degradation of the corner part of the resist pattern formed by using the main mask pattern is suppressed. In the case that the main mask pattern 10 becomes a light transmission area, inner serifs 16 are added respectively to two optional adjacent corner parts 20 and 22 of the main mask pattern 10 and an outer serif 18 is added to an edge part 24 held between the two corner parts 20 and 22 (in this case, in the case that the main mask pattern becomes a light shielding area, the outer serifs 18 are added to the respective two corner parts 20 and 22 and the inner serif 16 is added to the edge part 24). And the photomask, the exposure method and the semiconductor device are provided. COPYRIGHT: (C)2003,JPO

Correction method for mask pattern, photomask, exposure method and semiconductor device

An apparatus for baking a semiconductor wafer having a resist pattern thereon includes a baking oven in which the semiconductor wafer is placed and heated, and a first hot plate which is provided in the baking oven to heat an entire bottom surface of the semiconductor wafer. The apparatus also includes a gas supply unit having a gas introducing path, through which the purge gas is introduced into the baking oven, and a gas exhaust path, through which the purge gas is exhausted out of the baking oven. A gas temperature controller controls a temperature of the purge gas in order that the purge gas flowing around a peripheral edge or outer portion of the wafer has a higher temperature than that around the center or inner portion of the wafer.

Method and apparatus for performing baking treatment to semiconductor wafer

According to the present invention, a semiconductor device is fabricated by the following processes. First, a film to be etched is formed on a semiconductor substrate. On the film to be etched is formed a resist film. Then, a first pattern group including first patterns having a first size and a second pattern group including second patterns arranged outside of the first pattern group are formed by exposure. The resist film is then developed to form openings in the resist film so that the resultant openings correspond to the first and second patterns, respectively. The openings are then made smaller by annealing the resist film. The aforementioned processes enables openings having substantially the same shape to be formed in the film to be etched.

Katsuo Oshima

Papers

Mask pattern correction method

Method of manufacturing semiconductor device

Correction method for mask pattern, photomask, exposure method and semiconductor device

Method and apparatus for performing baking treatment to semiconductor wafer

Fabrication method for a semiconductor device