The progressively decreasing feature size of the circuit components has tremendously increased the need for the global surface planarization of the various thin film layers that constitute the integrated circuit (IC). Global planarization, being one of the major solutions to meet the demands of the industry, needs to be achieved following the most efficient polishing procedure. Chemical mechanical polishing (CMP) is the planarization method that has been selected by the semiconductor industry today. CMP, an ancient process used for glass polishing, was adopted first as a microelectronic fabrication process by IBM in the 80 s for SiO2 polishing. To achieve efficient planarization at miniaturized device dimensions, there is a need for a better understanding of the physics, chemistry and the complex interplay of tribo-mechanical phenomena occurring at the interface of the pad and wafer in presence of the fluid slurry medium. In spite of the fact that CMP research has grown by leaps and bounds, there are some teething problems associated with CMP process such as delamination, microscratches, dishing, erosion, corrosion, inefficient post-CMP clean, etc.; research on which is still developing. The fundamental understanding of the CMP is highly necessary to characterize, optimize and model the process. The CMP process is ready to make a positive impact on 30% of the US$ 135 billion global semiconductor market. This paper presents an overview of CMP process in general, the science and mechanism of polishing, different metal and dielectric CMP processes. The impact of consumables on the CMP process, post-CMP cleaning, modeling of different CMP processes as well as the future trends are also discussed.

Chemical mechanical planarization for microelectronics applications

A micro-contact and wear model for chemical-mechanical polishing of silicon wafers

Nano- to microscale wear and mechanical characterization using scanning probe microscopy

CMP of hard disk substrate using a colloidal SiO2 slurry: preliminary experimental investigation

The invention provides polishing pads for chemical-mechanical polishing comprising a porous foam and a method for their production. In one embodiment, the porous foam has an average pore size of about 50 μm or less, wherein about 75% or more of the pores have a pore size within about 20 μm or less of the average pore size. In another embodiment, porous foam has an average pore size of about 20 μm or less. In yet another embodiment, the porous foam has a multi-modal pore size distribution. The method of production comprises (a) combining a polymer resin with a supercritical gas to produce a single-phase solution and (b) forming a polishing pad from the single-phase solution, wherein the supercritical gas is generated by subjecting a gas to an elevated temperature and pressure.

Microporous polishing pads

Wear phenomena in chemical mechanical polishing

A polishing pad for polishing a semiconductor wafer which includes an open-celled, porous substrate having sintered particles of synthetic resin. The porous substrate is a uniform, continuous and tortuous interconnected network of capillary passage. The pores of the porous substrate have an average pore diameter of from about 5 to about 100 microns which enhances pad polishing performance.

Kaufman Frank B

Papers

Wear phenomena in chemical mechanical polishing

Polishing pad for semiconductor substrate