As the reliability is a critical issue for new generation multi-level cell (MLC) flash memories, there is growing call for fast and compact error correction code (ECC) circuit with minimum impact on memory access time and chip area. This paper presents a high-throughput and low-power ECC scheme for MLC NAND flash memories. The BCH encoder and decoder architecture features byte-wise processing and a low complexity key equation solver using a simplified Berlekamp-Massey algorithm. Resource sharing and power reduction techniques are also applied. Synthesized using 0.25-mum CMOS technology in a supply voltage of 2.5 V, the proposed BCH (4148,4096) encoder/decoder achieves byte-wise processing, and it needs an estimated cell area of 0.2 mm2, and an average power of 3.18 mW with 50 MB/s throughput

Low-Power High-Throughput BCH Error Correction VLSI Design for Multi-Level Cell NAND Flash Memories

This paper presents EC feature implemented by the authors in the test model of the draft ITUT video coding standard H.26L.The selected EC algorithms are based on weighted pixel value averaging for INTRA pictures and boundarymatchingbased motion vector recovery for INTER pictures. The specific concealment strategy and some special methods, including handling of Bpictures, multiple reference frames and entire frame losses, are described. Both subjective and objective results are given based on simulations under Internet conditions. The feature was adopted and is now included in the latest H.26L reference software TML9.0.

The Error Concealment Feature in the H.26L Test Model

Prior research efforts have been focusing on using BCH codes for error correction in multi-level cell (MLC) NAND flash memory. However, BCH codes often require highly parallel implementations to meet the throughput requirement. As a result, large area is needed. In this paper, we propose to use Reed-Solomon (RS) codes for error correction in MLC flash memory. A (828, 820) RS code has almost the same rate and length in terms of bits as a BCH (8248, 8192) code. Moreover, it has at least the same error-correcting performance in flash memory applications. Nevertheless, with 70% of the area, the RS decoder can achieve a throughput that is 121% higher than the BCH decoder. A novel bit mapping scheme using gray code is also proposed in this paper. Compared to direct bit mapping, our proposed scheme can achieve 0.02 dB and 0.2 dB additional gains by using RS and BCH codes, respectively, without any overhead.

Error correction for multi-level NAND flash memory using Reed-Solomon codes

Bit-error correction is crucial for realizing cost-effective and reliable NAND Flash-memory-based storage systems. In this paper, low-power and high-throughput error-correction circuits have been developed for multilevel cell (MLC) nand Flash memories. The developed circuits employ the Bose-Chaudhuri-Hocquenghem code to correct multiple random bit errors. The error-correcting codes for them are designed based on the bit-error characteristics of MLC NAND Flash memories for solid-state drives. To trade the code rate, circuit complexity, and power consumption, three error-correcting architectures, named as whole-page, sector-pipelined, and multistrip ones, are proposed. The VLSI design applies both algorithmic and architectural-level optimizations that include parallel algorithm transformation, resource sharing, and time multiplexing. The chip area, power consumption, and throughput results for these three architectures are presented.

VLSI Implementation of BCH Error Correction for Multilevel Cell NAND Flash Memory

A low-power, high-speed architecture which performs two-dimension forward and inverse discrete wavelet transform (DWT) for the set of filters in JPEG2000 is proposed by using a line-based and lifting scheme It consists of one row processor and one column processor each of which contains four sub-filters And the row processor which is time-multiplexed performs in parallel with the column processor Optimized shift-add operations are substituted for multiplications, and edge extension is implemented by an embedded circuit The whole architecture which is optimized in the pipeline design way to speed up and achieve higher hardware utilization has been demonstrated in FPGA Two pixels per clock cycle can be encoded at 100 MHz The architecture can he used as a compact and independent IP core for JPEG2000 VLSI implementation and various real-time image/video applications

Low-power and high-speed VLSI architecture for lifting-based forward and inverse wavelet transform

In this paper, a new high-speed VLSI architecture for decoding Reed-Solomon codes with the Berlekamp-Massey algorithm is presented. The proposed scheme uses the fully folded systolic architecture in which a single array of processors, computes both the error-locator and the error-evaluator polynomials. The proposed scheme utilizes the folding property of systolic array architectures and reduces the number of multipliers and adders drastically at the expense of some compromise in the speed. More interestingly, the proposed architecture requires approximately 60% fewer multipliers and a simpler control structure than the popular RiBM architecture. The reduction in the number of multipliers and adders in the proposed architecture leads to smaller silicon area and lower power consumption.

Ultra folded high-speed architectures for Reed Solomon decoders

The H.264 encoded video is highly sensitive to loss of motion vectors during transmission. Several statistical techniques are proposed for recovering such lost motion vectors. These use only the motion vectors that belong to the macroblocks that are horizontally or vertically adjacent to the lost macroblock, to recover the latter. Intuitively this is one of the main reasons behind why these techniques yield inferior solutions in scenarios where there is a non-linear motion. This paper proposes B-Spline based statistical techniques that comprehensively address the motion vector recovery problem in the presence of different types of motions that include slow, fast/sudden, continuous and non-linear movements. Testing the proposed algorithms with different benchmark video sequences shows an average improvement of up to 2 dB in the Peak Signal to Noise Ratio of some of the recovered videos, over existing techniques. A 2 dB improvement in PSNR is very significant from an application point of view.

Efficient Motion Vector Recovery Algorithm for H.264 Using B-Spline Approximation

This paper presents architectures and scheduling algorithms for the 2-D Discrete Wavelet Transform (DWT) and the Inverse Discrete Wavelet Transform (IDWT) using 9/7-tap filter banks based on the Non-expansive Symmetric Extension (NSE) scheme that reduces distortion at boundaries of the reconstructed image. The hardware has been implemented for image blocks of size 32/spl times/32 pixels, up to third level of transform, and cuts down the power consumption at the architecture level by incorporating three techniques, viz., Canonic Sign Digit (CSD) and common subexpression sharing technique, Gray code addressing mode and resource sharing. The implementation has been tested using 0.35 /spl mu/m (three metal) technology by simulation at functional, circuit and physical levels. The performance measures of implementation, viz., area, memory requirement, speed and power have been evaluated.

VLSI Implementation of 2-D DWT/IDWT Cores using 9/7-tap filter banks based on the Non-expansive Symmetric Extension Scheme

This paper describes a fully pipelined parallel architecture for the New Three Step Search (NTSS) hierarchical search block-matching algorithm for the estimation of small motions in video coding. Techniques for reducing external memory accesses are also developed. The proposed architecture produces efficient solution for real-time motion estimation required in video applications with low memory bandwidth requirement. This architecture is the best tradeoff in terms of hardware overload and speed among the all-existing Three Step Search (TSS) architectures and is also suitable for estimation of small motion in video coding. This architecture can be used for various video applications from low bit-rate video to HDTV systems.

A parallel architectural implementation of the New Three-Step Search algorithm for block motion estimation

This study proposes a novel motion vector recovery (MVR) algorithm for the H.264 video coding standard, which takes into account the change in the motion vectors (MVs) in different directions. Existing algorithms for MVR are confined to use the horizontal or vertical directions to recover the lost MVs. However, in the presence of non-linear movements or a fast/sudden motion of any object in a scene of the given input video, the MVs recovered by these algorithms turn out to be inaccurate. The proposed directional interpolation-based technique can interpolate the MVs in any direction based on the tendency of motion around the lost macro block, thus making it suitable to handle non-linear or fast motions. Testing the proposed technique with different benchmark video sequences shows an average improvement 1-2-dB in the peak signal-to-noise ratio of the recovered video over existing techniques.

Kavish Seth

Papers

Ultra folded high-speed architectures for Reed Solomon decoders

Efficient Motion Vector Recovery Algorithm for H.264 Using B-Spline Approximation

VLSI Implementation of 2-D DWT/IDWT Cores using 9/7-tap filter banks based on the Non-expansive Symmetric Extension Scheme

A parallel architectural implementation of the New Three-Step Search algorithm for block motion estimation

Efficient motion vector recovery algorithm for H.264 using directional interpolation