IEEE Transactions on Pattern Analysis and Machine Intelligence

Pattern recognition

A strain sensor has been fabricated from a polymer nanocomposite with multiwalled carbon nanotube (MWNT) fillers. The piezoresistivity
of this nanocomposite strain sensor has been investigated based on an improved three-dimensional (3D) statistical resistor network
model incorporating the tunneling effect between the neighboring carbon nanotubes (CNTs), and a fiber reorientation model. The
numerical results agree very well with the experimental measurements. As compared with traditional strain gauges, much higher sensitivity
can be obtained in the nanocomposite sensors when the volume fraction of CNT is close to the percolation threshold. For a small
CNT volume fraction, weak nonlinear piezoresistivity is observed both experimentally and from numerical simulation. The tunneling
effect is considered to be the principal mechanism of the sensor under small strains.

Tunneling effect in a polymer/carbon nanotube nanocompositestrain sensor

The paper provide a brief overview of electronic structure theory and details the implementation of quantum chemistry methods on a graphical processing unit. The paper also analyze algorithm performance in terms of floating-point operations and memory bandwidth, and assess the adequacy of single-precision accuracy for quantum chemistry applications.

Graphical Processing Units for Quantum Chemistry

Peak-to-average power-ratio (PAPR) reduction for OFDM systems is investigated in a probabilistic framework. A new constellation extension technique is developed whereby the data for each subcarrier are represented either by points in the original constellation or by extended points. An optimal representation of the OFDM signal is achieved by using a de-randomization algorithm where the conditional probability involved is handled by using the Chernoff bound and the evaluation of the many hyperbolic cosine functions involved is replaced by a tight upper bound for these functions. The proposed algorithm can be used by itself or be combined with a selective rotation technique described in the paper and with other known algorithms such as the coordinate descent optimization and selective mapping algorithms to achieve further performance enhancements at the cost of a slight increase in the computational complexity. When compared with other existing PAPR-reduction algorithms, the enhanced algorithm offers improved PAPR-reduction performance and improved computational complexity although, the transmit power is increased somewhat

/pdf/a-new-peak-to-average-power-ratio-reduction-algorithm-for-2twlktctqq.pdf

A New Peak-to-Average Power-Ratio Reduction Algorithm for OFDM Systems via Constellation Extension

Investigates different architectures implementing bit-parallel constant-coefficient multiplication in FPGA structures. First, multiplierless multiplication (MM) architectures employing canonic sign digit (CSD) and sub-structure sharing methods are addressed, and a novel algorithm for the conversion from two's-complement to CSD representation is presented. In the second part of this paper, lookup table-based multiplication (LM) is investigated. Correspondingly, the usage of different memory modules and finding the optimal combination of the memory and adders are considered. The LM architecture also considers reduction of the address width for each memory cell and the possibility of memory sub-structure sharing. Finally, implementation results for the Xilinx XC4000 and Virtex families are presented. As a result, MM generally surpasses the LM architecture. However, the actual choice between these two architectures is coefficient- and input parameter-dependent.

Constant coefficient multiplication in FPGA structures

PL-Grid: Foundations and Perspectives of National Computing Infrastructure. Integrating Various Grid Middleware Components and User Services into a Single Platform. Towards Professional Service Operations in Grids. New Capabilities in QosCosGrid Middleware for Advanced Job. Management, Advance Reservation and Co-allocation of Computing Resources - Quantum Chemistry Application Use Case Seamless Access to the PL-Grid e-Infrastructure Using UNICORE Middleware User-Oriented Provisioning of Secure Virtualized Infrastructure Flexible and Extendable Mechanism Enabling Secure Access to e-Infrastructures and Storage of Confidential Data for the GridSpace2 Virtual Laboratory. X Table of Contents SARA - System for Inventory and Static Security Control in a Grid Infrastructure. Security Best Practices: Applying Defense-in-Depth Strategy to Protect the NGI PL Automation of System Monitoring Based on Fuzzy Logic or Rules Comparison of Two Designed Approaches with Regard toComputational Infrastructures A Toolkit for Storage QoS Provisioning for Data-Intensive Applications Implementation of Service Level Management in PL-Grid Infrastructure. Highly Integrated Environment for Parallel Application Development Using QosCosGrid Middleware. User-Friendly Frameworks for Accessing Computational Resources Online Web-Based Science Gateway for Nanotechnology Research Scripting Language Extensions Offered by the GridSpace Experiment Platform Managing Entire Lifecycles of e-Science Applications in theGridSpace2 Virtual Laboratory - From Motivation through Idea to Operable Web-Accessible Environment Built on Top of PL-Grid e-Infrastructure. GridSpace2 Virtual Laboratory Case Study: Implementation of Algorithms for Quantitative Analysis of Grain Morphology in Self-assembled Hexagonal Lattices According to the Hillebrand Method.Examining Protein Folding Process Simulation and Searching for Common Structure Motifs in a Protein Family as Experiments in the GridSpace2 Virtual Laboratory. InSilicoLab - Managing Complexity of Chemistry Computations Ab Initio Molecular Dynamics Simulations of Ketocyanine Dyes in Organic Solvents.Polish Contribution to the Worldwide LHC Computing. PL-Grid e-Infrastructure for the Cherenkov Telescope Array Observatory. Training in the PL-Grid as Key Component to Attract Users to Grid e-Infrastructures. Dissemination Activities Conducted within the PL-Grid Project as a Successful Means of Promotion of Its Offer and Achievements.

Building a National Distributed e-Infrastructure–PL-Grid

Numerical simulations of elastic wave propagation using graphical processing units—Comparative study of high-performance computing capabilities

Most presented implementations of the exponential function confine to the single precision format. Increasing data width to the double precision format requires a different approach. The presented novel architecture employs three independent Look-Up Tables (LUTs) together with a short Taylor expansion exp(x)ap1+times. Implementation results show that the double precision exp() function implementation achieves huge performance with satisfactory accuracy, latency and FPGA area consumption.

FPGA Implementation of 64-Bit Exponential Function for HPC

This paper presents implementation of the double precision exponential function. A novel table-based architecture, together with short Taylor expansion, provides low latency (30 clock cycles) which is comparable to 32-bit implementations. Low area consumption of a single exp()module (roughtly 4% of XC4LX200) allows implementation of several parallel modules on a single FPGAs. The exp() function was implemented on the SGI RASC platform, thus external memory interface limitation allowed only a twin module parallelism. Each module is capable of processing at speed of 200 MHz with max. error of 1 ulp, RMSE equals 0,62. This implementation aims primarily to meet quantum chemistry's huge and strict requirements of precision and speed.

https://link.springer.com/content/pdf/10.1007/978-3-540-78610-8_28.pdf

Kazimierz Wiatr

Papers

Constant coefficient multiplication in FPGA structures

Building a National Distributed e-Infrastructure–PL-Grid

Numerical simulations of elastic wave propagation using graphical processing units—Comparative study of high-performance computing capabilities

FPGA Implementation of 64-Bit Exponential Function for HPC

Highly Efficient Structure of 64-Bit Exponential Function Implemented in FPGAs