Showing papers by "Kazumasa Nomoto published in 2002"
Patent•
17 Jul 2002TL;DR: In this paper, a semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array, serving also as gate electrodes of word transistors in a same row, extending in a row direction, and repeating in a column direction, is described.
Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.
53 citations
11 Jun 2002
TL;DR: In this article, a 2-bit/cell MONOS memory structure with a wrapped gate was proposed, where both programming and erasing are performed by source-side hot-electron injection and hot-hole injection, respectively.
Abstract: We have proposed a novel 2-bit/cell MONOS memory structure that features a wrapped gate. Programming and erasing are by source-side hot-electron injection and hot-hole injection, respectively. With this device, programming speeds <1 /spl mu/s with a programming current <2 /spl mu/A//spl mu/m, and erasing speeds <10 /spl mu/s have been achieved.
42 citations
Patent•
15 Jul 2002
TL;DR: In this paper, the authors proposed a method to reduce manufacturing cost by enhancing a common feature of a structure involving a memory transistor and a memory peripheral circuit, where a plurality of insulated gate transistors consisting the memory peripheral circuits and the memory transistor are formed on a single semiconductor substrate.
Abstract: PROBLEM TO BE SOLVED: To reduce manufacturing cost by enhancing a common feature of a structure involving a memory transistor and a memory peripheral circuit SOLUTION: A plurality of insulated gate transistors consisting the memory peripheral circuit and the memory transistor (formation region 10c) are formed on a single semiconductor substrate 10 The memory transistor is formed between the substrate 10 and a gate electrode 25 provided with a plurality of stacked films (charge storage film 14m) comprising therein a discrete charge storage means (charge trap) which is charged when storing or eliminating information Among the plurality of insulated gate transistors, at least a gate insulating film 14 which is formed between the substrate 10 and a gate electrode 23 or 24 and belongs to a high voltage transistor (formation region 10b) having the highest voltage in the memory peripheral circuit, has the same structure (three layers 14a-14c) as the charge storage film 14m COPYRIGHT: (C)2004,JPO
5 citations