An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost A method for manufacturing a semiconductor device includes the following steps: forming a semiconductor film; irradiating a laser beam by passing the laser beam through a photomask including a shield for shielding the laser beam; subliming a region which has been irradiated with the laser beam through a region in which the shield is not formed in the photomask in the semiconductor film; forming an island-shaped semiconductor film in such a way that a region which is not irradiated with the laser beam is not sublimed because it is a region in which the shield is formed in the photomask; forming a first electrode which is one of a source electrode and a drain electrode and a second electrode which is the other one of the source electrode and the drain electrode; forming a gate insulating film; and forming a gate electrode over the gate insulating film

Method for Manufacturing Semiconductor Device

Large last-level caches (L3Cs) are frequently used to bridge the performance and power gap between processor and memory. Although traditional processors implement caches as SRAMs, technologies such as STT-RAM (MRAM), and eDRAM have been used and/or considered for the implementation of L3Cs. Each of these technologies has inherent weaknesses: SRAM is relatively low density and has high leakage current; STT-RAM has high write latency and write energy consumption; and eDRAM requires refresh operations. As future processors are expected to have larger last-level caches, the goal of this paper is to study the trade-offs associated with using each of these technologies to implement L3Cs. In order to make useful comparisons between SRAM, STTRAM, and eDRAM L3Cs, we model them in detail and apply low power techniques to each of these technologies to address their respective weaknesses. We optimize SRAM for low leakage and optimize STT-RAM for low write energy. Moreover, we classify eDRAM refresh-reduction schemes into two categories and demonstrate the effectiveness of using dead-line prediction to eliminate unnecessary refreshes. A comparison of these technologies through full-system simulation shows that the proposed refresh-reduction method makes eDRAM a viable, energy-efficient technology for implementing L3Cs.

https://terpconnect.umd.edu/~blj/papers/hpca2013.pdf

Technology comparison for large last-level caches (L 3 Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM

At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above film formation condition, crystallization is not sufficiently attained in a crystallization process. By forming the amorphous silicon film using silane gas diluted with hydrogen, crystallization is sufficiently attained in the crystallization process even with the continuous formation of the base film through the amorphous silicon film in the single film forming chamber.

Method of Manufacturing a Semiconductor Device

The present invention generally provides a precleaning process prior to metallization for submicron features on substrates. The method includes cleaning the submicron features with radicals from a plasma of a reactive gas such as oxygen, a mixture of CF 4 /O 2 , or a mixture of He/NF 3 , wherein the plasma is preferably generated by a remote plasma source and the radicals are delivered to a chamber in which the substrate is disposed. Native oxides remaining in the submicron features are preferably reduced in a second step by treatment with radicals from a plasma containing hydrogen. Following the first or both precleaning steps, the features can be filled with metal by available metallization techniques which typically include depositing a barrier/liner layer on exposed dielectric surfaces prior to deposition of aluminum, copper, or tungsten. The precleaning and metallization steps can be conducted on available integrated processing platforms.

Reactive preclean prior to metallization for sub-quarter micron application

An array of memory cells configured to store at least one bit per one F 2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt 1 ) and a second voltage threshold region (Vt 2 ) and such that the programmed cell operates at reduced drain source current.

NROM memory cell, memory array, related devices and methods

Hot-carrier-induced device degradation has been studied for quarter-micrometer level buried-channel PMOSFETs. It was found that the major hot-carrier degradation mode for these small devices is quite different from that previously reported, which was caused by trapped electrons injected into the gate oxide. The new degradation mode is caused by the effect of interface traps generated by hot hole injection into the oxide near the drain in the saturation region. DC device lifetime for the new mode can be evaluated using substrate current rather than gate current as a predictor. Interface-trap generation due to hot-hole injection will become the dominant degradation mode in future PMOSFETs. >

New hot-carrier degradation mode and lifetime prediction method in quarter-micrometer PMOSFET

Copper metallization was applied to quarter-micron CMOS circuits using copper chemical vapor deposition (CVD) and chemical mechanical polishing (CMP). Both the metallization process and the electrical characteristics of CMOS devices/circuits were evaluated. Process-induced metal contamination on both sides of the wafer were quantitatively evaluated and reduced to about of 10/sup 11/ atoms/cm/sup 2/ by using an optimized cleaning sequence. The ability of borophosphosilicate-glass (BPSG) to act as a copper diffusion barrier was discovered and the ability of TiN to do so was also confirmed. Electrical characteristics of n and p MOSFET's with copper interconnections were stable even after annealing at 550/spl deg/C. The leakage current of the pn junction, capacitance-voltage characteristics and time-dependent dielectric breakdown characteristics of the MOS diode indicate that the copper metallization process did not deteriorate the pn junction and the gate oxide. Normal operation of a 53-stage quarter-micron CMOS inverter ring oscillator with copper metallization was successfully achieved.

Evaluation of a copper metallization process and the electrical characteristics of copper-interconnected quarter-micron CMOS

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory in which the number of times of verifying is less, a time of a write-in cycle including verifying or an erasure cycle is short, and power consumption is less. SOLUTION: In a memory cell array MCA, a plurality of dielectric films comprising a discrete level for storing information as quantity of captured electric charges have a plurality of memory cells laminated between a semiconductor in which a channel is formed and a control electrode. A column control circuit CC accesses to a memory cell of which the number is less than the number of memory cells in a write-in unit (e.g. memory cell connected to one word line) with which write-in is performed simultaneously, verification and read-out are performed, depending on the result, it is decided whether write-in (or erasure) is performed correctly in a corresponding write-in unit or not. A memory cell performing this verification/read-out may be provided separately, or a memory cell of one part of the memory cell array MCA can be used. COPYRIGHT: (C)2003,JPO

Non-volatile semiconductor memory

We have proposed a novel 2-bit/cell MONOS memory structure that features a wrapped gate. Programming and erasing are by source-side hot-electron injection and hot-hole injection, respectively. With this device, programming speeds <1 /spl mu/s with a programming current <2 /spl mu/A//spl mu/m, and erasing speeds <10 /spl mu/s have been achieved.

http://www.vlsisymposium.org/Past/02web/technology/tec_pdf/T21p1.pdf

A novel 2-bit/cell MONOS memory device with a wrapped-control-gate structure that applies source-side hot-electron injection

A semiconductor device capable of reducing a cell area without affecting the accuracy, capable of reducing the number of interconnection layers, and capable of realizing a hybrid circuit of a memory cell and peripheral circuit easily and at a low cost, including a bit line, a word line, control gate line, a capacitor with a first electrode connected to the word line, a read transistor comprising an NMOS connected between the bit line and a predetermined potential point and with a gate electrode connected to a second electrode of a capacitor, and a write transistor comprising an NMOS connected between the bit line and the second electrode of the capacitor and with a gate electrode connected to the control gate line.

T. Kobayashi

Papers

New hot-carrier degradation mode and lifetime prediction method in quarter-micrometer PMOSFET

Evaluation of a copper metallization process and the electrical characteristics of copper-interconnected quarter-micron CMOS

Non-volatile semiconductor memory

A novel 2-bit/cell MONOS memory device with a wrapped-control-gate structure that applies source-side hot-electron injection

Semiconductor device having a memory cell with a plurality of active elements and at least one passive element