Large grain data flow (LGDF) programming is natural and convenient for describing digital signal processing (DSP) systems, but its runtime overhead is costly in real time or cost-sensitive applications. In some situations, designers are not willing to squander computing resources for the sake of programmer convenience. This is particularly true when the target machine is a programmable DSP chip. However, the runtime overhead inherent in most LGDF implementations is not required for most signal processing systems because such systems are mostly synchronous (in the DSP sense). Synchronous data flow (SDF) differs from traditional data flow in that the amount of data produced and consumed by a data flow node is specified a priori for each input and output. This is equivalent to specifying the relative sample rates in signal processing system. This means that the scheduling of SDF nodes need not be done at runtime, but can be done at compile time (statically), so the runtime overhead evaporates. The sample rates can all be different, which is not true of most current data-driven digital signal processing programming methodologies. Synchronous data flow is closely related to computation graphs, a special case of Petri nets. This self-contained paper develops the theory necessary to statically schedule SDF programs on single or multiple processors. A class of static (compile time) scheduling algorithms is proven valid, and specific algorithms are given for scheduling SDF systems onto single or multiple processors.

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Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing

Bandwidth-efficient data transmission over telephone and radio channels is made possible by the use of adaptive equalization to compensate for the time dispersion introduced by the channel Spurred by practical applications, a steady research effort over the last two decades has produced a rich body of literature in adaptive equalization and the related more general fields of reception of digital signals, adaptive filtering, and system identification. This tutorial paper gives an overview of the current state of the art in adaptive equalization. In the first part of the paper, the problem of intersymbol interference (ISI) and the basic concept of transversal equalizers are introduced followed by a simplified description of some practical adaptive equalizer structures and their properties. Related applications of adaptive filters and implementation approaches are discussed. Linear and nonlinear receiver structures, their steady-state performance and sensitivity to timing phase are presented in some depth in the next part. It is shown that a fractionally spaced equalizer can serve as the optimum receive filter for any receiver. Decision-feedback equalization, decision-aided ISI cancellation, and adaptive filtering for maximum-likelihood sequence estimation are presented in a common framework. The next two parts of the paper are devoted to a discussion of the convergence and steady-state properties of least mean-square (LMS) adaptation algorithms, including digital precision considerations, and three classes of rapidly converging adaptive equalization algorithms: namely, orthogonalized LMS, periodic or cyclic, and recursive least squares algorithms. An attempt is made throughout the paper to describe important principles and results in a heuristic manner, without formal proofs, using simple mathematical notation where possible.

https://ieeexplore.ieee.org/iel5/35/23767/01090994.pdf

Adaptive equalization

A system of distributing video and/or audio information employs digital signal processing to achieve high rates of data compression. The compressed and encoded audio and/or video information is sent over standard telephone, cable or satellite broadcast channels to a receiver specified by a subscriber of the service, preferably in less than real time, for later playback and optional recording on standard audio and/or video tape.

Audio and video transmission and receiving system

A public switched telephone network (PSTN) provides digital video signals from a video information provider or digital service bureau to one or more of a plurality of subscriber premises. Administration of orders from subscribers is carried out by a video gateway and file servers at the central office. Asymmetrical digital subscriber line interface (ADSL) units over a local loop carry the necessary signalling between the subscribers and information providers. The interface units frequency multiplex digital video information with voice information to the subscriber and support transmission of a reverse control channel from the subscriber to the central office for transmission back to the information provider. Several enhancements and special features are disclosed.

Video-on-demand services using public switched telephone network

Practical echo cancellation techniques, in particular, those used in telecommunications, are reviewed. The various situations in which echoes are generated are examined. Echo path modeling techniques and adaptive algorithms for coefficient control are reviewed. Current international standardization activities are discussed, and echo canceler implementation considerations are set forth. These include echo cancelers for telephone circuits, echo cancelers for full-duplex data transmission over voice channels, acoustic echo cancelers, and echo cancelers for ISDN digital loop transmission. >

Echo cancellation and applications

An information communication system having a plurality of terminal equipment units, a network termination unit, a receive (R) line, and transmit (T) line. The terminal equipment units are commonly connected to the R and T line so as to communicate with the network termination unit. The communication is achieved in the form of successive frame signals, each composed of at least successive channels. Each terminal equipment determines a delay time for channel insertion into the frame signal on the T line. the delay time is determined during a learning identification algorithm operation which takes the transmission delay time along the R and T lines into consideration.

Method and apparatus for adjusting channel insertion timing

This paper describes a newly developed CMOS LSI DSP (FDSP3). It has a powerful multiplier, which operates at a rate of 10 M-operations/s, almost twice as fast as the fastest existing LSI DSP's. Some key techniques to attain these high performance characteristics of the DSP are described. Suitable memory capacities of the RAM and ROM were analyzed as a function of the operational capability of the DSP. These were reflected in the design of the FDSP3. To assist in the development of the program, support tools have been developed. A Pascal based cross compiler and an on-line debugging tool are described in some detail.

A High Performance LSI Digital Signal Processor for Communication

Disclosed is a frame synchronizing apparatus in a receiving equipment for receiving digital signals for PCM communication. The digital signals consist serial signals at a rate of f₀ (bps). The serial signals include a frame synchronizing signal constituting n bits or a part of the frame synchronizing signal, collectively arranged in one frame. To attain a high-speed operation and a shorter synchronization establishing time, the apparatus comprises a latching circuit (101) for converting the serial signals into parallel signals and for latching the parallel signals, and a circuit (102) for detecting a plural number of times of synchronization during the n bit interval in one frame.

Frame synchronizing apparatus

A device for discriminating between two values of a signal using DC offset compensation including an automatic gain control circuit, a peak detector circuit and a feedback path from the peak detector circuit to the input circuit of the automatic gain control circuit. The value of the feedback current is regulated so that the maximum value of one of the same polarity signals and the opposite polarity signal coincides with the minimum value of the other of the two signals.

Kazuo Murano

Papers

Echo cancellation and applications

Method and apparatus for adjusting channel insertion timing

A High Performance LSI Digital Signal Processor for Communication

Frame synchronizing apparatus

Device for discriminating between two values of a signal with DC offset compensation